memory-model

Clarify Rust memory-ordering semantics for ARM64 concurrency patterns.

58|4|Updated Mar 8, 2026
One-click install
npx skills add https://github.com/po4yka/RIPDPI --skill memory-model-po4yka
Or copy as Structured Prompt for Agent
Please help me install this Agent Skill.
Skill: memory-model
Source: https://github.com/po4yka/RIPDPI/tree/main/.claude/skills/memory-model
Command: npx skills add https://github.com/po4yka/RIPDPI --skill memory-model-po4yka

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

Guiding developers through Rust memory ordering on ARM64 Android, focusing on happens-before reasoning, ordering constraints, and fence usage to prevent data races.

Core Features & Use Cases

  • Clear explanations of Relaxed, Acquire, Release, AcqRel, and SeqCst semantics in the Rust atomics API.
  • Practical patterns for on-device concurrency in RIPDPI across crates like telemetry, ws-tunnel, and dns-resolver.
  • Use Case: when reviewing concurrent code, identify safe memory-order choices for cross-thread communication and synchronization.

Quick Start

Review your concurrent Rust code and apply the recommended memory-ordering rules to ensure correctness on ARM64.

Frequently Asked Questions about memory-model

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I choose the correct Rust memory ordering on ARM64 to prevent data races?

Choosing the correct Rust memory ordering on ARM64 requires applying happens-before reasoning to Relaxed, Acquire, Release, AcqRel, and SeqCst operations. This ensures proper visibility and synchronization for safe cross-thread communication.

What is the difference between Acquire and Release memory ordering in Rust concurrent code?

Acquire ordering ensures subsequent reads see modifications made before a corresponding Release store. This pairing establishes a happens-before relationship, preventing data races by guaranteeing visibility of shared state across threads.

When do I need to use SeqCst instead of AcqRel for Rust atomic operations?

SeqCst provides a global total order for all sequentially consistent operations, while AcqRel only applies acquire and release semantics locally. SeqCst is necessary when cross-thread synchronization requires a universally agreed-upon operation sequence.

How do I place memory fences for safe cross-thread communication in Rust?

Placing memory fences in Rust involves inserting Acquire and Release barriers to enforce visibility ordering without blocking execution. Proper fence placement establishes happens-before relationships, preventing data races in concurrent Rust code.

Does Relaxed memory ordering cause data races in Rust ARM64 concurrency?

Relaxed memory ordering does not inherently cause data races, but it provides no synchronization or ordering guarantees. It is safe only for independent atomic counter increments where cross-thread visibility of surrounding memory operations is unnecessary.