model-compute-simulation

Run the simulator with your model name, batch size, sequence length, TP/EP settings, GPU type, dtype, and measured forward-pass latency via --measured-ms. MFU is computed as theoretical minimum time divided by measured time, using peak FLOPS from the GPU specs table.

Extract per-kernel durations from a torch profiler trace into JSON, then pass it with --kernel-flow to get a kernel-level MFU table mapping each kernel to its operator, FLOPs, and MFU. Kernels in moe and gemm_fp8 categories use the fp8 peak FLOPS denominator.

The config index covers DeepSeek-V3/V4-Flash, Qwen3-235B-A22B, Qwen3.6-35B-A3B, Qwen3.8-27B, Kimi-K2/K2.5, MiniMax-M2/M3, and GLM-5. GPU specs include H20, H100 SXM 80GB, H200 SXM 141GB, and B200 SXM 180GB, with aliases like h100 or b200.

Not directly. You must provide the model's config.json so its parameters can be verified or added to model-config-index.json before running estimates, since the architecture parameters determine the entire operator sequence.

FLOPs require Input Dims in the trace, which only exist when the profiler runs with record_shapes=True. CUDA Graph replay also omits per-iteration cpu_op events, so eager-mode traces are recommended for full coverage.

Traces show post-TP-split dimensions rather than full-model shapes, scope attribution degrades without with_stack=True, and compiled or graph-replayed kernels may lack shape data. The documented fallback is reading the model's forward() in SGLang, vLLM, or TensorRT-LLM source.