open-verifier

What problem does it solve?

Automates end-to-end VLSI verification of Verilog/SystemVerilog designs by running linting, testbench generation, simulation, and reporting autonomously, delivering a clean verification report and waveforms with minimal user intervention.

Core Features & Use Cases

• Environment checks to confirm Verilator, Icarus Verilog, and GTKWave are installed, plus a deterministic lint pass.
• Automatic testbench generation that exercises the DUT comprehensively, including edge cases and stimulus.
• End-to-end simulation with Icarus Verilog and waveform viewing support via GTKWave, followed by a structured verification report.
• Handles hierarchical designs by recursively analyzing src/ to understand top-level DUT and sub-module interfaces.
• Suitable for CI-like workflows and interactive debugging when user decisions are required.

Quick Start

Place your Verilog/SystemVerilog DUT in src/ and ask the agent to verify it end-to-end.