open-verifier

Name: open-verifier
Availability: InStock
Author: aryaman9999

Automate end-to-end Verilog/SystemVerilog verification with linting, simulation, and reporting.

6|Updated Apr 11, 2026

Search Tags:#verification #simulation #systemverilog #waveforms #verilog #tb-generation

Ready to run

npx skills add https://github.com/Aryaman9999/open-verifier --skill open-verifier

💬 Prompt for ChatGPT / Claude Chat▼

Please help me install this Agent Skill.
Skill: open-verifier
Source: https://github.com/Aryaman9999/open-verifier/tree/main/.agents/skills/open-verifier
Command: npx skills add https://github.com/Aryaman9999/open-verifier --skill open-verifier

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes scripts (resource) components.

What problem does it solve?

Automates end-to-end VLSI verification of Verilog/SystemVerilog designs by running linting, testbench generation, simulation, and reporting autonomously, delivering a clean verification report and waveforms with minimal user intervention.

Core Features & Use Cases

Environment checks to confirm Verilator, Icarus Verilog, and GTKWave are installed, plus a deterministic lint pass.
Automatic testbench generation that exercises the DUT comprehensively, including edge cases and stimulus.
End-to-end simulation with Icarus Verilog and waveform viewing support via GTKWave, followed by a structured verification report.
Handles hierarchical designs by recursively analyzing src/ to understand top-level DUT and sub-module interfaces.
Suitable for CI-like workflows and interactive debugging when user decisions are required.

Quick Start

Place your Verilog/SystemVerilog DUT in src/ and ask the agent to verify it end-to-end.

Frequently Asked Questions about open-verifier

High-intent search queries and answers about installing and using this skill.

FAQPage Schema

How do I automate Verilog verification end-to-end for my design?▼

Automating Verilog verification involves running environment checks, deterministic linting, automatic testbench generation, and simulation with Icarus Verilog to produce a structured report and waveforms.

Does this verification flow support hierarchical SystemVerilog DUTs?▼

Hierarchical SystemVerilog DUTs are supported by recursively analyzing the src/ directory to understand top-level interfaces and sub-module connections during testbench generation and simulation.

Can I use GTKWave to view waveforms generated during SystemVerilog simulation?▼

GTKWave is fully supported for waveform viewing, allowing you to visually inspect the signal outputs generated after running end-to-end simulations with Icarus Verilog for interactive debugging.

Do I need Verilator installed to run automated Verilog testbench generation?▼

Verilator is required for the initial environment checks and deterministic lint pass, which validate the design before automatically generating testbenches and proceeding to simulation with Icarus Verilog.

What is the best way to handle linting and simulation for Verilog in a CI workflow?▼

Linting and simulation for Verilog in CI workflows are handled autonomously through environment checks, deterministic lint passes, and automated testbench generation that exercises edge cases before producing a verification report.

Why does my Verilog simulation fail during automatic testbench generation for complex designs?▼

Simulation failures during automatic testbench generation may occur if environment checks fail for Verilator or Icarus Verilog, or if the recursive analysis of hierarchical DUT interfaces in src/ encounters structural issues.