p2-arch-design

What problem does it solve?

This Skill automates the transition from Phase 1 research to Phase 2 hardware architecture by reviewing algorithm candidates for hardware feasibility, designing block-level data paths, and producing a validated architecture and reference C model ready for downstream RTL work.

Core Features & Use Cases

• Candidate HW Feasibility Review: Analyze Phase 1 algorithm outputs and identify which candidates are implementable in hardware given iron requirements and resource constraints.
• Block-level Data Path & Architecture Design: Produce block diagrams, data paths, and interfaces that map algorithmic functions to hardware blocks.
• Parallel Reference C Model & Iterative Review: Build a reference C model in parallel with architecture design and run a 3-round review cycle to finalize artifacts.
• Use Case: Take a researched algorithm for a signal-processing pipeline and convert it into a compliant block-level architecture with an accompanying C reference model and review records for RTL handoff.

Quick Start

Run the p2-arch-design skill to evaluate Phase 1 outputs, design block-level data paths, build a reference C model, and generate docs/phase-2-architecture artifacts.