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p2-arch-design

Evaluate Phase 1 algorithm candidates for hardware feasibility and design block-level data-path architectures.

43|9|Updated Feb 25, 2026
Search Tags:#orchestrator#rtl#architecture-design#requirements-traceability#block-design#hardware-feasibility#reference-c-model
One-click install
npx skills add https://github.com/babyworm/rtl-agent-team --skill p2-arch-design
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: p2-arch-design
Source: https://github.com/babyworm/rtl-agent-team/tree/main/skills/p2-arch-design
Command: npx skills add https://github.com/babyworm/rtl-agent-team --skill p2-arch-design

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This Skill automates the transition from Phase 1 research to Phase 2 hardware architecture by reviewing algorithm candidates for hardware feasibility, designing block-level data paths, and producing a validated architecture and reference C model ready for downstream RTL work.

Core Features & Use Cases

  • Candidate HW Feasibility Review: Analyze Phase 1 algorithm outputs and identify which candidates are implementable in hardware given iron requirements and resource constraints.
  • Block-level Data Path & Architecture Design: Produce block diagrams, data paths, and interfaces that map algorithmic functions to hardware blocks.
  • Parallel Reference C Model & Iterative Review: Build a reference C model in parallel with architecture design and run a 3-round review cycle to finalize artifacts.
  • Use Case: Take a researched algorithm for a signal-processing pipeline and convert it into a compliant block-level architecture with an accompanying C reference model and review records for RTL handoff.

Quick Start

Run the p2-arch-design skill to evaluate Phase 1 outputs, design block-level data paths, build a reference C model, and generate docs/phase-2-architecture artifacts.

Frequently Asked Questions about p2-arch-design

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I transition algorithm research into block-level hardware architecture for RTL design?▼

To transition algorithm research into block-level hardware architecture, evaluate Phase 1 algorithm candidates for hardware feasibility, design block-level data paths, and generate validated architecture artifacts ready for RTL implementation.

What is the process for evaluating hardware feasibility of algorithm candidates?▼

Evaluating hardware feasibility involves analyzing Phase 1 algorithm outputs against iron requirements and resource constraints, verifying REQ-A-* constraints, and identifying which candidates are implementable in hardware.

How do I build a reference C model alongside block-level architecture design?▼

You can build a reference C model in parallel with block-level architecture design, running a three-round iterative review cycle to finalize artifacts and resolve open Phase 1 items before RTL handoff.

Can I use this architecture design workflow for signal-processing pipeline hardware projects?▼

Yes, this block-level architecture design workflow applies to RTL hardware projects like signal-processing pipelines, converting researched algorithms into compliant data-path architectures with accompanying reference C models and review records.

What artifacts and documentation are generated during Phase 2 hardware architecture design?▼

Phase 2 hardware architecture design generates block diagrams, data paths, interface mappings, reference C models, and review records under docs/phase-2-architecture and reviews/phase-2-architecture directories.

What's the best way to ensure requirements traceability during hardware architecture design?▼

To ensure requirements traceability during hardware architecture design, verify REQ-A-* constraints, resolve open Phase 1 items, and maintain compliance with iron requirements throughout the three-round architecture review process.

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