patent-diagram-generator

Generate patent-style flowcharts, block diagrams, and architecture diagrams with Graphviz.

167|28|Updated Nov 15, 2025
One-click install
npx skills add https://github.com/RobThePCGuy/Claude-Patent-Creator --skill patent-diagram-generator
Or copy as Structured Prompt for Agent
Please help me install this Agent Skill.
Skill: patent-diagram-generator
Source: https://github.com/RobThePCGuy/Claude-Patent-Creator/tree/main/skills/patent-diagram-generator
Command: npx skills add https://github.com/RobThePCGuy/Claude-Patent-Creator --skill patent-diagram-generator

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill requires graphviz, and includes references (resource) components.

What problem does it solve?

Creating professional, USPTO-compliant technical diagrams for patent applications is a specialized and often manual task. This Skill automates the generation of various diagram types, saving time and ensuring consistency and accuracy in your patent figures.

Core Features & Use Cases

  • Flowchart Generation: Create method step flowcharts and decision trees for method claims.
  • Block Diagram Creation: Generate system component and hardware architecture diagrams for system claims.
  • Patent-Style Formatting: Add reference numbers (10, 20, 30, etc.) and use clear labels for professional USPTO filing.
  • Use Case: A patent agent needs to quickly create a block diagram for a system claim. They can provide the components and connections, and the skill will output a high-quality SVG diagram with automatic reference numbering, ready for inclusion.

Quick Start

Create a block diagram for a system with an input sensor, a central processor, memory storage, and an output display, showing their connections.

Frequently Asked Questions about patent-diagram-generator

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I generate patent diagrams with reference numbering for USPTO filings?

Patent diagrams with reference numbering are generated using Graphviz to render technical flowcharts, block diagrams, and system architectures. This Skill automates the creation of USPTO-compliant figures by applying standard reference numbers (10, 20, 30, etc.) and professional formatting to your diagram specifications, producing SVG, PNG, or PDF output ready for patent applications.

Can I create method-claim flowcharts and system-claim block diagrams in the same workflow?

Yes. This Skill supports both diagram types within a single workflow. Method claims render as decision-tree flowcharts showing process steps, while system claims render as block diagrams showing component architecture and connections. Both automatically apply patent-style reference numbering and clear labeling for professional USPTO submissions.

What output formats does Graphviz rendering support for patent diagrams?

Graphviz rendering outputs patent diagrams in SVG, PNG, and PDF formats. SVG provides scalable vector graphics suitable for editing and web display, PNG offers raster resolution for document embedding, and PDF delivers publication-ready files for direct USPTO filing and printing.

Do I need Graphviz installed to generate these patent technical diagrams?

Yes, Graphviz is required as a dependency. The Skill uses Graphviz's layout and rendering engine to process your diagram specifications and produce the final patent-style figures with reference numbering and professional formatting.

How do I add clear labels and connections between components in block diagrams?

Specify your components and their connections in your input; the Skill applies Graphviz layout algorithms to automatically position nodes and render edges with clear visual connections. Reference numbers are applied to each component, and labels are rendered with professional spacing and alignment for USPTO compliance.

What are the limitations when creating complex system architectures with many interconnected components?

Graphviz layout effectiveness depends on diagram complexity and node count. Highly interconnected systems may produce dense or overlapping layouts; layout algorithms can be adjusted, but extremely large or heavily circular architectures may require manual refinement or diagram restructuring to maintain clarity and USPTO readability standards.