perf-optimization

To coordinate CUDA Graph and Triton kernel optimizations safely, establish a baseline benchmark first, apply changes through specialist routing, validate correctness after modifications, and roll back if regressions occur.

The best way to tune TileIR or CuTe DSL kernels is running an iterative optimize-profile loop that measures baseline performance, delegates tuning to specialists, analyzes bottlenecks, and validates before-and-after metrics.

Yes, the performance optimization workflow supports remote SLURM cluster execution by ensuring cluster allocations are reused across specialists through a shared context block during kernel generation and profiling.

To validate PTX kernel performance metrics, enforce a safe modification workflow that requires baseline measurement, backs up code before editing, validates changes against the baseline, and rolls back if regressions appear.

You should avoid autopilot-driven iterative optimization loops when you lack a baseline benchmark to measure against, or when your environment cannot support the required backup-edit-validate-rollback safety workflow.

Yes, you can improve model latency across multiple backend improvements simultaneously by routing CUDA Graph, Triton, TileIR, and CuTe DSL tasks to the correct specialists while maintaining a single coordinated optimization loop.