quartus-flow

What problem does it solve?

This Skill makes Quartus FPGA/SoC projects reproducible by letting you create projects, apply global settings, run the full compile flow, and extract reports using Tcl instead of a GUI workflow.

Core Features & Use Cases

• Reproducible Quartus project creation: Builds a project from Tcl with predictable device/family, top entity, and file lists.
• End-to-end compilation automation: Runs synthesis/place-and-route via execute_flow -compile suitable for CI.
• Report extraction for downstream decisions: Generates timing/area/power artifacts to gate builds and track regressions.
• Inference-oriented RTL patterns: Helps steer memory (M10K/M20K BRAM) and DSP inference through appropriate SystemVerilog constructs.

Quick Start

Use the quartus-flow skill to generate a Tcl script that creates a Quartus project for a given top module, sets the target device and SDC constraints, compiles with execute_flow -compile, and writes timing/area reports into a reports directory.