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riscv-rtl-lint

Generate Verilog from Scala/Chisel via sbt and lint with Verilator.

Updated Mar 18, 2026
Search Tags:#sbt#lint#rtl#verilator#verilog#riscv#rtl-generation
One-click install
npx skills add https://github.com/etewe333/eda_first --skill riscv-rtl-lint
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: riscv-rtl-lint
Source: https://github.com/etewe333/eda_first/tree/main/.claude/skills/riscv-rtl-lint
Command: npx skills add https://github.com/etewe333/eda_first --skill riscv-rtl-lint

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

RISC-V RTL 构建和语法检查技能，帮助自动化流水线在生成 Verilog RTL 代码后执行 Verilator 语法检查，提升设计验证效率。

Core Features & Use Cases

  • RTL 构建: 使用 sbt 生成 Verilog RTL 代码并输出到 generated/ 目录，验证结果可靠性。
  • 语法检查: 使用 Verilator 进行 lint 检查，指定顶层模块并捕获潜在问题。
  • Use Case: 在 RISC-V 项目中将模块从 Gen 生成到 Verilog 文件并进行语法把关，确保设计进入后续仿真阶段。

Quick Start

Run sbt "runMain <Module>Gen" to generate RTL and place Verilog files in generated/, then lint with Verilator using --top-module <Module>.

Frequently Asked Questions about riscv-rtl-lint

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I automate Verilog generation and Verilator linting for RISC-V RTL?▼

You can automate Verilog generation and Verilator linting for RISC-V RTL by running sbt to generate code into the generated directory, then executing Verilator with the --top-module flag. This pipeline ensures deterministic build and syntax validation.

Why does Verilator report MULTITOP errors when linting generated Chisel Verilog?▼

Verilator reports MULTITOP errors when linting generated Chisel Verilog because multiple top modules exist. You can resolve this by specifying a single top module using the Verilator --top-module flag during the RISC-V lint check.

What is the process to generate Verilog from Scala or Chisel for RISC-V designs?▼

Generating Verilog from Scala or Chisel for RISC-V designs involves running the sbt command with your module generator, which outputs the synthesized Verilog RTL files into a designated generated directory for subsequent linting and simulation.

Can I use Verilator to lint RISC-V RTL without specifying a top module?▼

You cannot reliably lint RISC-V RTL with Verilator without specifying a top module, as doing so risks MULTITOP errors. Applying the --top-module flag ensures Verilator targets the correct generated Verilog hierarchy for accurate syntax checks.

How do I integrate RTL build and syntax checks into a deterministic RISC-V pipeline?▼

Integrating RTL build and syntax checks into a deterministic RISC-V pipeline requires sequencing sbt Verilog generation into a generated directory followed by Verilator lint execution, ensuring consistent design validation before simulation.

Does this RTL lint workflow require additional dependencies beyond sbt and Verilator?▼

This RTL lint workflow requires no additional dependencies beyond sbt and Verilator. It uses your existing Scala or Chisel environment to generate Verilog and performs syntax checks directly within the standard RISC-V build toolchain.

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