riscv-testbench-compile

What problem does it solve?

RV32I RTL verification requires a robust testbench and an efficient build flow. This skill automates the generation of a Verilator-based C++ testbench and the compilation of the simulation executable, consolidating two essential steps into a single workflow for RV32I designs.

Core Features & Use Cases

• Testbench generation: produce a compliant Verilator C++ testbench, verify the generated header (V<module>.h) port definitions, ensure the presence of required functions such as double sc_time_stamp() { return 0; }, and generate test cases with programmatic expected-value calculation and standardized logging.
• Simulation compilation: invoke verilator --cc to compile Verilog sources, link the C++ testbench, and produce an executable simulator while using a proper temporary directory to avoid permission issues.
• Verification strategy: align with the RV32I two's complement wrap-around rules and include edge-case scenarios to validate arithmetic wrap-around, signed comparisons, and zero flag behavior.

Quick Start

生成 Verilator C++ testbench 并编译 RV32I 模块的仿真可执行文件。