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riscv-testbench-compile

Generate Verilator C++ testbenches and compile RV32I simulation executables.

Updated Mar 18, 2026
Search Tags:#verification#simulation#compile#rtl#testbench#verilator#riscv
One-click install
npx skills add https://github.com/etewe333/eda_first --skill riscv-testbench-compile
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: riscv-testbench-compile
Source: https://github.com/etewe333/eda_first/tree/main/.claude/skills/riscv-testbench-compile
Command: npx skills add https://github.com/etewe333/eda_first --skill riscv-testbench-compile

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

RV32I RTL verification requires a robust testbench and an efficient build flow. This skill automates the generation of a Verilator-based C++ testbench and the compilation of the simulation executable, consolidating two essential steps into a single workflow for RV32I designs.

Core Features & Use Cases

  • Testbench generation: produce a compliant Verilator C++ testbench, verify the generated header (V<module>.h) port definitions, ensure the presence of required functions such as double sc_time_stamp() { return 0; }, and generate test cases with programmatic expected-value calculation and standardized logging.
  • Simulation compilation: invoke verilator --cc to compile Verilog sources, link the C++ testbench, and produce an executable simulator while using a proper temporary directory to avoid permission issues.
  • Verification strategy: align with the RV32I two's complement wrap-around rules and include edge-case scenarios to validate arithmetic wrap-around, signed comparisons, and zero flag behavior.

Quick Start

生成 Verilator C++ testbench 并编译 RV32I 模块的仿真可执行文件。

Frequently Asked Questions about riscv-testbench-compile

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I generate a Verilator C++ testbench for RV32I RTL modules?▼

To generate a Verilator testbench for RV32I RTL, this automation inspects the V<module>.h header to confirm port definitions and produces a compliant C++ testbench with programmatic expected-value calculation and standardized logging.

What is the best way to compile a Verilator simulation executable for RV32I designs?▼

Compiling a Verilator simulation executable for RV32I involves invoking verilator --cc on Verilog sources, linking the C++ testbench, and building the simulator binary in a proper temporary directory to avoid permission issues.

Does RV32I testbench generation handle two's complement wrap-around and arithmetic edge cases?▼

RV32I testbench generation aligns with two's complement wrap-around rules and includes edge-case scenarios to validate arithmetic wrap-around, signed comparisons, and zero flag behavior.

Do I need Verilator installed to compile RV32I RTL simulation binaries?▼

Yes, Verilator is required as the primary tool to compile RV32I RTL sources, link the generated C++ testbench, and produce the deterministic simulation executable.

Why does my Verilator testbench compilation fail with permission issues?▼

Verilator compilation encounters permission issues when using improper working directories; this workflow resolves it by linking and building the simulation executable in a designated temporary directory.

What functions are required in a Verilator C++ testbench for RV32I verification?▼

A Verilator C++ testbench for RV32I verification requires the double sc_time_stamp() function and port definitions verified against the V<module>.h header to ensure deterministic simulation execution.

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