Convert Zotero paper hardware descriptions into synthesizable SystemVerilog RTL code.
npx skills add https://github.com/czh-ee-2023/zotero-aris --skill rtl-author
Please help me install this Agent Skill. Skill: rtl-author Source: https://github.com/czh-ee-2023/zotero-aris/tree/main/.claude/skills/rtl-author Command: npx skills add https://github.com/czh-ee-2023/zotero-aris --skill rtl-author
This Skill automates the process of writing SystemVerilog RTL code from research paper hardware descriptions, streamlining the transition from paper to practical implementation.
Generate RTL code for the hardware architecture described in the paper 'PaperTitle' using the command: /rtl-author PaperTitle
High-intent search queries and answers about installing and using this skill.
You can generate SystemVerilog RTL code by extracting hardware architecture descriptions from Zotero papers and converting them into synthesizable code. This specifically targets digital design workflows for CIM, LUT accelerators, and macro designs.
Yes, you can convert Compute-in-Memory (CIM) architecture papers into synthesizable SystemVerilog RTL. The tool specifically supports digital CIM hardware, LUT accelerators, and macro designs described in Zotero papers.
Yes, you need the Zotero MCP integration to extract hardware architecture descriptions from papers. The extracted text is then processed to produce synthesizable SystemVerilog RTL code for digital design workflows.
The best way to create testbench stubs is to generate them alongside synthesizable SystemVerilog RTL code directly from a paper's hardware architecture description, specifically supporting LUT accelerators and macro designs.
This paper-to-RTL approach works primarily for specific targeted hardware, particularly Compute-in-Memory (CIM), LUT accelerators, and digital CIM macro designs described in academic papers.
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codejunkie99Apply SystemVerilog assertions, covergroups, and testbench templates to validate RTL designs.
amoslee2026Translate MAS, FSM, and datapath specifications into synthesizable SystemVerilog RTL.
RedClausGuide SystemVerilog testbench design with layered architectures and verification methodologies.
