rtl-author

What problem does it solve?

This Skill automates the process of writing SystemVerilog RTL code from research paper hardware descriptions, streamlining the transition from paper to practical implementation.

Core Features & Use Cases

• Paper-to-RTL Conversion: Converts hardware architecture descriptions from Zotero papers into synthesizable SystemVerilog RTL code.
• Targeted Hardware: Supports CIM (Compute-in-Memory) hardware, LUT accelerators, and digital CIM macro designs.
• Use Case: When you need to implement a paper's hardware architecture in HDL, this skill can generate the necessary RTL code and testbench stubs.

Quick Start

Generate RTL code for the hardware architecture described in the paper 'PaperTitle' using the command: /rtl-author PaperTitle