rtl-design

What problem does it solve?

This Skill addresses the challenges of RTL development, including module planning, coding standards enforcement, lint checking, CDC/RDC analysis, and synthesis readiness verification, ensuring efficient and high-quality RTL code.

Core Features & Use Cases

• Module Planning: Top-down decomposition for clear responsibility and domain identification.
• Coding Standards: Enforces industry-standard SystemVerilog coding practices.
• Lint Checking: Identifies and resolves latches, incomplete sensitivity lists, undriven outputs, and other issues.
• CDC/RDC Analysis: Ensures proper handling of clock-domain crossing and reset domains.
• Synth Check: Verifies synthesis readiness, including timing, area, and critical paths.

Quick Start

Run the RTL design flow for my AXI DMA controller block using the 'rtl-design' skill.