rtl-document

What problem does it solve?

Generate accurate, up-to-date module-level documentation directly from RTL source and available synthesis reports to eliminate manual drift between implementation and docs and accelerate reviews and integration.

Core Features & Use Cases

• Extracts ports, parameters, FSM states, instance lists, and header comments from SystemVerilog source to produce structured Markdown per module.
• Incorporates synthesis area and timing summaries when synth reports exist and preserves complex width expressions without modifying source files.
• Flags naming-convention violations (port prefixes, clock/reset names, instance prefixes) and documents missing header descriptions, enabling quick compliance checks before release.

Quick Start

Generate documentation for module cabac_encoder by reading rtl/cabac_encoder/cabac_encoder.sv and any syn reports and write docs/rtl/cabac_encoder.md using the provided template.