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rtl-document

Generate module-level Markdown documentation from SystemVerilog RTL sources and synthesis reports.

43|9|Updated Feb 25, 2026
Search Tags:#documentation#synthesis#code-analysis#naming-conventions#ports#rtl#systemverilog
One-click install
npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-document
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: rtl-document
Source: https://github.com/babyworm/rtl-agent-team/tree/main/skills/rtl-document
Command: npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-document

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Generate accurate, up-to-date module-level documentation directly from RTL source and available synthesis reports to eliminate manual drift between implementation and docs and accelerate reviews and integration.

Core Features & Use Cases

  • Extracts ports, parameters, FSM states, instance lists, and header comments from SystemVerilog source to produce structured Markdown per module.
  • Incorporates synthesis area and timing summaries when synth reports exist and preserves complex width expressions without modifying source files.
  • Flags naming-convention violations (port prefixes, clock/reset names, instance prefixes) and documents missing header descriptions, enabling quick compliance checks before release.

Quick Start

Generate documentation for module cabac_encoder by reading rtl/cabac_encoder/cabac_encoder.sv and any syn reports and write docs/rtl/cabac_encoder.md using the provided template.

Frequently Asked Questions about rtl-document

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I generate module-level documentation from SystemVerilog source files?▼

SystemVerilog documentation generation extracts ports, parameters, FSM states, and instance lists from source files to produce structured Markdown. It preserves complex width expressions and writes output to docs/rtl without modifying the original source.

Can I automatically extract synthesis area and timing summaries into my RTL docs?▼

Yes, you can extract synthesis area and timing summaries into RTL docs. When synthesis reports are available, the documentation generator incorporates these metrics directly into the per-module Markdown output to accelerate design reviews and release preparation.

What is the best way to check naming conventions across my hardware RTL project?▼

The best way to check naming conventions is to flag violations during documentation generation. This process checks port prefixes, clock and reset names, and instance prefixes against expected standards, while also documenting any missing header descriptions before release.

Does RTL documentation generation preserve complex width expressions in port tables?▼

Yes, RTL documentation generation preserves complex width expressions in port tables. When extracting ports and parameters from SystemVerilog source files, the tool retains the original expression syntax instead of flattening or simplifying the widths.

How do I create FSM listings and instance summaries for a design review?▼

To create FSM listings and instance summaries for a design review, apply this generation task to your hardware RTL project. It reads the SystemVerilog source to extract finite state machine states and hierarchical module instances into structured Markdown.

What limitations exist when generating documentation from RTL source and synthesis reports?▼

A key limitation is that documentation generation requires available synthesis reports to include area and timing metrics; without them, only source-derived data is extracted. Additionally, the tool only writes Markdown files and strictly does not modify your RTL source files.

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