rtl-p5s-sva-check

What problem does it solve?

This Skill extracts SystemVerilog Assertions from RTL and executes a SymbiYosys-based formal verification flow to prove or disprove temporal and safety properties, generating per-property pass/fail results and counterexamples for diagnosis.

Core Features & Use Cases

• Assertion extraction: Locates and emits SVA properties into formal/*.sv assertion files suitable for formal engines.
• Engine orchestration: Orchestrates sv2v conversion when needed, selects SymbiYosys engines for BMC and induction, and manages multi-round refinement.
• Reporting and diagnosis: Produces a formal_verify.json summarizing proof outcomes and assists with counterexample analysis for failing properties.
• Use Case: Prove handshake invariants, FIFO safety properties, or FSM invariants exhaustively when simulation cannot cover all corner cases.

Quick Start

Run SVA formal verification on the target module to extract assertions, execute SymbiYosys BMC and induction, and produce a formal_verify.json summary.