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rtl-p5s-sva-check

Extract SystemVerilog assertions from RTL and run SymbiYosys formal verification.

43|9|Updated Feb 25, 2026
Search Tags:#assertions#formal-verification#rtl#bmc#sva#symbiyosys#sv2v
One-click install
npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-p5s-sva-check
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: rtl-p5s-sva-check
Source: https://github.com/babyworm/rtl-agent-team/tree/main/skills/rtl-p5s-sva-check
Command: npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-p5s-sva-check

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

This Skill extracts SystemVerilog Assertions from RTL and executes a SymbiYosys-based formal verification flow to prove or disprove temporal and safety properties, generating per-property pass/fail results and counterexamples for diagnosis.

Core Features & Use Cases

  • Assertion extraction: Locates and emits SVA properties into formal/*.sv assertion files suitable for formal engines.
  • Engine orchestration: Orchestrates sv2v conversion when needed, selects SymbiYosys engines for BMC and induction, and manages multi-round refinement.
  • Reporting and diagnosis: Produces a formal_verify.json summarizing proof outcomes and assists with counterexample analysis for failing properties.
  • Use Case: Prove handshake invariants, FIFO safety properties, or FSM invariants exhaustively when simulation cannot cover all corner cases.

Quick Start

Run SVA formal verification on the target module to extract assertions, execute SymbiYosys BMC and induction, and produce a formal_verify.json summary.

Frequently Asked Questions about rtl-p5s-sva-check

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I run formal verification on SystemVerilog assertions to prove RTL properties?▼

Run formal verification on SystemVerilog assertions by extracting SVA properties from RTL into assertion files, then executing SymbiYosys engines for BMC and induction to exhaustively prove or disprove safety properties.

What is the best way to exhaustively check FIFO safety properties when simulation cannot cover all corner cases?▼

Exhaustively check FIFO safety properties by extracting SystemVerilog assertions and running SymbiYosys-based formal verification, which proves invariants across all reachable states without relying on directed simulation testbenches.

Do I need sv2v to run SymbiYosys formal verification on SystemVerilog repositories?▼

You need sv2v conversion when your SystemVerilog RTL requires translation for the selected SymbiYosys formal engines, ensuring compatibility for BMC and induction property proving.

How does BMC and induction prove or disprove temporal properties in RTL designs?▼

BMC and induction prove temporal properties by having SymbiYosys engines exhaustively explore state spaces, checking bounded reachability and unbounded invariants to find counterexamples for failing assertions.

How do I diagnose counterexamples from failing SystemVerilog assertions during formal verification?▼

Diagnose counterexamples from failing assertions by reviewing the formal_verify.json summary, which reports per-property pass/fail status and provides counterexample traces for detailed analysis.

Can I use this formal verification flow on SystemVerilog repositories with lint errors?▼

This formal verification flow applies to lint-clean SystemVerilog repositories, requiring pre-validated code to ensure accurate assertion extraction and reliable SymbiYosys property proving.

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