rtl-p5s-sva-policy

What problem does it solve?

Provides clear, project-level SVA coding conventions, iterative property refinement rules, and engine guidance so verification engineers can produce consistent, provable SystemVerilog assertions and actionable formal results.

Core Features & Use Cases

• SVA coding conventions: naming for signals and clocks, use of logic, and descriptive assertion labels to ensure assertions match RTL ports and project style.
• Iterative refinement protocol: minimum three-round property extraction and strengthening process covering safety, protocol, edge cases, and liveness.
• Engine and run guidance: SymbiYosys engine recommendations, sv2v handling notes, timeout/escalation rules, and a final checklist to produce formal_verify.json with counterexample handling.
• Use Case: Use when preparing formal/*.sv properties and .sby runs to ensure assertions are non-vacuous, properly constrained, and compatible with automated formal flows.

Quick Start

Use this policy to audit and prepare SVA properties, enforce naming and assume/assert rules, and generate the formal_verify.json checklist before running SymbiYosys.