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rtl-p5s-sva-policy

Define SVA coding conventions and iterative formal verification workflows for RTL designs.

43|9|Updated Feb 25, 2026
Search Tags:#assertions#formal-verification#systemverilog#sva#symbiyosys#verification-policy
One-click install
npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-p5s-sva-policy
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: rtl-p5s-sva-policy
Source: https://github.com/babyworm/rtl-agent-team/tree/main/skills/rtl-p5s-sva-policy
Command: npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-p5s-sva-policy

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Provides clear, project-level SVA coding conventions, iterative property refinement rules, and engine guidance so verification engineers can produce consistent, provable SystemVerilog assertions and actionable formal results.

Core Features & Use Cases

  • SVA coding conventions: naming for signals and clocks, use of logic, and descriptive assertion labels to ensure assertions match RTL ports and project style.
  • Iterative refinement protocol: minimum three-round property extraction and strengthening process covering safety, protocol, edge cases, and liveness.
  • Engine and run guidance: SymbiYosys engine recommendations, sv2v handling notes, timeout/escalation rules, and a final checklist to produce formal_verify.json with counterexample handling.
  • Use Case: Use when preparing formal/*.sv properties and .sby runs to ensure assertions are non-vacuous, properly constrained, and compatible with automated formal flows.

Quick Start

Use this policy to audit and prepare SVA properties, enforce naming and assume/assert rules, and generate the formal_verify.json checklist before running SymbiYosys.

Frequently Asked Questions about rtl-p5s-sva-policy

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I write SystemVerilog assertions for formal verification?▼

SystemVerilog assertions for formal verification require standardized coding conventions, including specific signal and clock naming, logic type usage, and descriptive labels to ensure properties match RTL ports and project style.

What is the best way to refine SVA properties to avoid vacuity in SymbiYosys?▼

Refining SVA properties to avoid vacuity in SymbiYosys involves an iterative three-round protocol covering safety, protocol, edge cases, and liveness, while balancing assume and assert constraints.

How do I handle sv2v conversion when running formal verification scripts?▼

Handle sv2v conversion during formal verification by relying on formal scripts to manage the translation, ensuring SystemVerilog properties remain compatible with automated formal flows without manual intervention.

Why does my SymbiYosys formal verification timeout or fail on complex SVA checks?▼

SymbiYosys formal verification times out or fails on complex SVA checks when properties lack proper constraints; escalation rules for timeouts and missing tools guide engine selection and iterative property strengthening.

Can I use SymbiYosys engines for both safety and liveness checks in SystemVerilog?▼

SymbiYosys engines support both safety and liveness checks in SystemVerilog by applying engine recommendations and iterative property strengthening to produce actionable formal results and counterexamples.

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