Triage RTL/VCS failures via log analysis, waveform inspection, and JIRA correlation.
npx skills add https://github.com/rajivhasija79-bit/DV-Skills --skill rtl-sim-debug
Please help me install this Agent Skill. Skill: rtl-sim-debug Source: https://github.com/rajivhasija79-bit/DV-Skills/tree/main/rtl-sim-debug Command: npx skills add https://github.com/rajivhasija79-bit/DV-Skills --skill rtl-sim-debug
Debugging and triaging RTL/VCS failures across DV flows by orchestrating log triage, waveform inspection, and domain-dispatch into specialized sub-skills.
Provide a failing sim log, RTL DV tree, and a JIRA corpus to kick off end-to-end RTL/VCS failure triage.
High-intent search queries and answers about installing and using this skill.
Triage UVM_ERROR and VCS simulation failures by orchestrating log triage, waveform inspection, and JIRA regression history correlation. The skill structures issue writeups and dispatches analysis to domain sub-skills for targeted debugging across large RTL hierarchies.
To debug an RTL simulation hang or X-propagation issue, you need a failing sim log, the RTL DV tree, and a JIRA corpus. These inputs allow the skill to reproduce failures, detect triggers, and correlate regression history for structured issue writeups.
Waveform inspection assists RTL VCS log triage by providing visual signal analysis alongside automated log parsing. This combination helps identify assertion failures and trace X-propagation roots across complex DV flows during end-to-end failure triage.
Yes, you can correlate simulation failures with JIRA regression history. The skill processes a JIRA corpus alongside a failing sim log to match current UVM_ERROR or hang occurrences with previously documented issues for accelerated issue resolution.
Dispatch to domain sub-skills for targeted RTL failure analysis when specific triggers are detected during the initial log triage and waveform inspection. This targeted approach handles large RTL hierarchies by routing UVM_FATAL or assertion issues to specialized subsystem skills for resolution.
babywormGenerate minimal SystemVerilog testbenches and analyze VCD waveforms to isolate RTL failures.
Euraika-LabsMap test coverage to GDD critical paths and audit regression tests for bug fixes.
babywormRun UVM-based verification on RTL with commercial simulators and merge coverage artifacts.
htlin222Search and analyze log files and codebases for error patterns and stack traces.
