rtl-sim-debug
CommunityOrchestrates RTL/VCS failure triage end-to-end.
Authorrajivhasija79-bit
Version1.0.0
Installs0
System Documentation
What problem does it solve?
Debugging and triaging RTL/VCS failures across DV flows by orchestrating log triage, waveform inspection, and domain-dispatch into specialized sub-skills.
Core Features & Use Cases
- Phase-driven intake for RTL/VCS failures (UVM_ERROR/UVM_FATAL, hangs, assertions, X-propagation).
- Automatic domain dispatch to rtl-sim-debug-<subsystem> skills for targeted analysis.
- JIRA/regression-history correlation and structured writeups to accelerate issue resolution.
- Waveform and log-assisted triage across large RTL hierarchies.
Quick Start
Provide a failing sim log, RTL DV tree, and a JIRA corpus to kick off end-to-end RTL/VCS failure triage.
Dependency Matrix
Required Modules
None requiredComponents
scriptsreferences
💻 Claude Code Installation
Recommended: Let Claude install automatically. Simply copy and paste the text below to Claude Code.
Please help me install this Skill: Name: rtl-sim-debug Download link: https://github.com/rajivhasija79-bit/DV-Skills/archive/main.zip#rtl-sim-debug Please download this .zip file, extract it, and install it in the .claude/skills/ directory.
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