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rtl-synth-check

Run Yosys synthesis estimation to detect latches and unmapped cells.

43|9|Updated Feb 25, 2026
Search Tags:#synthesis#asic#yosys#sdc#nand2#area-estimation#latch-detection
One-click install
npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-synth-check
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: rtl-synth-check
Source: https://github.com/babyworm/rtl-agent-team/tree/main/skills/rtl-synth-check
Command: npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-synth-check

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes scripts (resource) and references (resource) components.

What problem does it solve?

Provides early, technology-mapped synthesis feedback to catch unsynthesizable RTL constructs, inferred latches, and unmapped cells while producing area and timing estimates before costly tool signoff.

Core Features & Use Cases

  • SDC-first flow: generates and validates SDC constraints before synthesis to ensure timing-aware optimization.
  • ASIC-mapped estimation: runs Yosys with NangateOpenCellLibrary (NanGate45 proxy for TSMC 28nm) to report area in NAND2-FO2 equivalents and produce structured PPA summaries.
  • Robust validation: detects inferred latches (hard-fail), checks memory inference, and writes syn/summary.json for downstream automation and reporting.
  • Use case: run pre-tapeout estimations to compare area impact of RTL changes and ensure SDC coverage for Design Compiler or Genus ingestion.

Quick Start

Run SDC-first synthesis estimation for the top module and write syn/summary.json using the rtl-synth-check skill.

Frequently Asked Questions about rtl-synth-check

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I estimate ASIC gate area before synthesis signoff?▼

RTL pre-synthesis verification detects inferred latches, unmapped cells, and unsynthesizable constructs by running Yosys-based synthesis estimation. It hard-fails on inferred latches and checks memory inference to ensure RTL readiness before tapeout.

How does SDC-driven timing-aware synthesis estimation work?▼

SDC-driven timing-aware synthesis estimation generates and validates SDC constraints before running Yosys to ensure timing-aware optimization. The flow requires SDC generation upfront to produce accurate area and timing summaries mapped to NanGate45.

Can I use Yosys with NanGate45 as a TSMC 28nm proxy for area estimation?▼

Yosys supports NanGate45 liberty mapping as a proxy for TSMC 28nm area estimation. It runs technology-mapped synthesis and converts the results into NAND2-FO2 gate equivalents to provide early PPA summaries for ASIC RTL projects.

How do I convert SystemVerilog to Verilog for Yosys synthesis estimation?▼

SystemVerilog to Verilog conversion uses sv2v support before running Yosys synthesis estimation. This allows ASIC RTL projects with SystemVerilog source files to undergo SDC-first synthesis checks and NanGate45 mapping successfully.

Why does Yosys synthesis estimation fail on unmapped cells?▼

Yosys synthesis estimation fails on unmapped cells when RTL constructs cannot map to the NanGate45 liberty library. The robust validation detects these unmapped cells during technology mapping to prevent unsynthesizable RTL from passing pre-synthesis checks.

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