rtl-synth-check

What problem does it solve?

Provides early, technology-mapped synthesis feedback to catch unsynthesizable RTL constructs, inferred latches, and unmapped cells while producing area and timing estimates before costly tool signoff.

Core Features & Use Cases

• SDC-first flow: generates and validates SDC constraints before synthesis to ensure timing-aware optimization.
• ASIC-mapped estimation: runs Yosys with NangateOpenCellLibrary (NanGate45 proxy for TSMC 28nm) to report area in NAND2-FO2 equivalents and produce structured PPA summaries.
• Robust validation: detects inferred latches (hard-fail), checks memory inference, and writes syn/summary.json for downstream automation and reporting.
• Use case: run pre-tapeout estimations to compare area impact of RTL changes and ensure SDC coverage for Design Compiler or Genus ingestion.

Quick Start

Run SDC-first synthesis estimation for the top module and write syn/summary.json using the rtl-synth-check skill.