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soc-security-skills

Analyze SoC hardware security with STRIDE threat modeling and SVA verification.

1|1|Updated Feb 21, 2026
Search Tags:#verification#threat modeling#compliance#microarchitecture#side-channel#soc security#hardware security
One-click install
npx skills add https://github.com/dtsong/claude-code-windows-setup --skill soc-security-skills
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: soc-security-skills
Source: https://github.com/dtsong/claude-code-windows-setup/tree/main/skills/soc-security
Command: npx skills add https://github.com/dtsong/claude-code-windows-setup --skill soc-security-skills

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes scripts (resource) and references (resource) and assets (resource) components.

What problem does it solve?

This Skill provides a comprehensive suite of tools for hardware security engineers to systematically analyze and document the security posture of System-on-Chip (SoC) components and architectures.

Core Features & Use Cases

  • End-to-End Security Analysis: Covers threat modeling, verification scaffolding, compliance mapping, and executive briefing.
  • Advanced Threat Detection: Includes specialized skills for microarchitectural attacks, physical side-channel analysis, kernel security, and emerging hardware paradigms.
  • Formal Verification Support: Enables formalization of security properties using TLA+.
  • Use Case: A hardware security engineer needs to assess the security of a new crypto engine. They can use the pipeline to threat model it, generate verification assertions, map it against FIPS 140-3, and brief the CISO on the findings.

Quick Start

Use the soc-security pipeline to perform a full security analysis of the TDISP device assignment flow.

Frequently Asked Questions about soc-security-skills

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I perform hardware threat modeling for SoC components using STRIDE?▼

Hardware threat modeling for SoC components applies the STRIDE methodology to identify security risks and structures findings using attack trees. This approach systematically exposes vulnerabilities across chip architectures before cloud integration.

What's the best way to generate verification scaffolding for hardware security analysis?▼

Verification scaffolding for hardware security analysis generates SystemVerilog Assertions (SVA) templates to formalize security properties. This creates a structured testing framework to validate SoC component behaviors against identified threats.

Can I map SoC security compliance against FIPS 140-3 and ISO 21434 standards?▼

SoC security compliance mapping checks architecture against standards like FIPS 140-3 and ISO 21434. This process aligns hardware security controls with regulatory requirements to produce a structured compliance profile.

How does TLA+ formal specification support SoC security verification?▼

TLA+ formal specification supports SoC security verification by mathematically defining hardware security properties. This formalization uncovers design flaws in microarchitectural attacks and side-channel analysis that traditional testing misses.

When do I need physical side-channel analysis for SoC security?▼

Physical side-channel analysis is needed when securing SoC components against microarchitectural attacks that extract cryptographic data. This analysis detects hardware vulnerabilities exploitable through power, timing, or electromagnetic emissions.

Does this SoC security methodology cover kernel security and emerging hardware paradigms?▼

This SoC security methodology covers kernel security, emerging hardware paradigms, and TDISP device assignment flows. It provides specialized threat modeling and executive briefing capabilities for these advanced architectural domains.

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