Optimize C struct layouts for performance, alignment, and ABI stability.
npx skills add https://github.com/zzxyb/wlframe --skill struct-layout
Please help me install this Agent Skill. Skill: struct-layout Source: https://github.com/zzxyb/wlframe/tree/main/.github/copilot/skills/struct-layout Command: npx skills add https://github.com/zzxyb/wlframe --skill struct-layout
This Skill addresses the complexities of designing and reviewing C struct layouts, ensuring optimal performance through careful field ordering, alignment, and cache locality. It helps prevent common pitfalls like poor memory access patterns and ABI instability.
Review the proposed layout for the 'wlf_texture' struct to ensure hot fields are not buried behind cold metadata.
High-intent search queries and answers about installing and using this skill.
Optimizing C struct layout for cache locality involves carefully ordering fields so hot-path data is grouped together, minimizing padding through proper alignment, and placing cold metadata separately to prevent cache misses during frequent access.
To maintain ABI stability when ordering fields in a C struct, keep public layouts backward compatible by placing new fields at the end or using implementation pointers to hide internal state, ensuring existing binaries continue functioning without recompilation.
C struct padding occurs because the compiler inserts empty bytes to satisfy alignment requirements for specific data types, which can fragment memory and cause poor cache locality if frequently accessed hot fields are interspersed with unused padding gaps.
Placing intrusive list nodes or implementation pointers inside a C struct requires positioning them based on usage patterns, typically grouping internal linkage and hidden state away from public ABI-sensitive fields to balance maintainability and access speed.
Reviewing an existing C struct layout identifies cache miss issues by analyzing field grouping and alignment, ensuring hot-path data is not buried behind cold metadata, and rectifying padding to improve overall memory access patterns and performance.
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