svlinter

What problem does it solve?

This Skill automates the process of linting, analyzing, and querying SystemVerilog hardware design files, helping to identify errors and understand design structure.

Core Features & Use Cases

• Linting: Detects errors, warnings, and style issues in SystemVerilog code.
• AST Export: Generates Abstract Syntax Trees (AST) or Concrete Syntax Trees (CST) for design analysis.
• Instance Querying: Filters and searches for module instances within the design hierarchy.
• Use Case: Quickly check your RTL design for common errors before synthesis or simulation by running a full lint check.

Quick Start

Use the svlinter skill to lint the design files listed in 'design.f' and output the report to the 'work/' directory.