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svlinter

Performs SystemVerilog linting, AST generation, and module instance querying via filelist input.

1|1|Updated Jun 15, 2023
Search Tags:#linting#ast#rtl#systemverilog#hardware design#svlinter
One-click install
npx skills add https://github.com/Paradicat/demo --skill svlinter
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: svlinter
Source: https://github.com/Paradicat/demo/tree/main/agent_pack/skills/svlinter
Command: npx skills add https://github.com/Paradicat/demo --skill svlinter

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

This Skill automates the process of linting, analyzing, and querying SystemVerilog hardware design files, helping to identify errors and understand design structure.

Core Features & Use Cases

  • Linting: Detects errors, warnings, and style issues in SystemVerilog code.
  • AST Export: Generates Abstract Syntax Trees (AST) or Concrete Syntax Trees (CST) for design analysis.
  • Instance Querying: Filters and searches for module instances within the design hierarchy.
  • Use Case: Quickly check your RTL design for common errors before synthesis or simulation by running a full lint check.

Quick Start

Use the svlinter skill to lint the design files listed in 'design.f' and output the report to the 'work/' directory.

Frequently Asked Questions about svlinter

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I lint SystemVerilog RTL designs before synthesis?▼

You can lint SystemVerilog designs by running static analysis on a filelist of source files, optionally specifying a top-level module. This detects errors, warnings, and style issues in your RTL code.

What does static analysis of SystemVerilog reveal about hardware design structure?▼

Static analysis generates Abstract Syntax Trees (AST) and Concrete Syntax Trees (CST) to represent your SystemVerilog design structure. It also queries and filters module instances within the design hierarchy.

How do I export an Abstract Syntax Tree from SystemVerilog files?▼

Export an Abstract Syntax Tree (AST) by processing your SystemVerilog source filelist through static analysis. The tool supports outputting the AST in various formats like JSONL and text.

Do I need a top-level module to query module instances in SystemVerilog?▼

A top-level module is optional for querying module instances. Providing it alongside your source filelist helps filter and search the design hierarchy more comprehensively during static analysis.

Can I run multiple subcommands for comprehensive SystemVerilog design checks?▼

Yes, you can run multiple subcommands for comprehensive SystemVerilog design checks. This combines linting, AST generation, and instance querying into a single execution for thorough static analysis.

What output formats are supported for SystemVerilog linting reports?▼

Supported output formats for SystemVerilog linting reports include JSONL and text. These formats allow easy integration of static analysis results into your existing hardware design workflows.

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