What problem does it solve?
This Skill removes the guesswork in orchestrating a correct Synopsys ASIC front-end flow by providing tool-specific, end-to-end procedures that produce reliable netlists and reports.
Core Features & Use Cases
- Design Compiler synthesis (compile_ultra): Turn RTL into a gate-level netlist with QoR-focused reporting for timing, area, and power.
- VCS simulation: Compile and run RTL/netlist simulations with consistent compile/run commands for regression sanity checks.
- SpyGlass lint + CDC: Run linting and clock-domain-crossing verification and capture actionable reports.
- DFT Compiler scan insertion: Configure scan parameters, perform DFT DRC, insert scan logic, and generate scan netlists.
- VC Formal property proving: Load Verilog and SVA assertions and run formal proof runs with property reporting.
Use case example: You need an ASIC RTL implementation that must synthesize cleanly, simulate without regressions, pass lint/CDC checks, support scan insertion for DFT, and prove key protocol properties—using the same project structure and validation gates to catch issues early.
Quick Start
Use the synopsys-flow skill to generate the complete Synopsys flow commands for DC/VCS/SpyGlass/DFT Compiler/VC Formal for your project, given your top module, RTL sources, constraints, assertions, and expected outputs.
