synthesis-guidelines

What problem does it solve?

This Skill helps you avoid RTL patterns and synthesis setup mistakes that cause failed synthesis, poor QoR, timing violations, and gate-level simulation surprises.

Core Features & Use Cases

• Synthesis-friendly RTL checklist: enforces correct sequential/combinational coding (always_ff/always_comb defaults), avoids latch and combinational-loop inference, and prevents sim-vs-synth mismatches.
• Pragmatic attribute and constraint guidance: shows how to apply synthesis attributes/directives (Vivado and DC/Genus equivalents) and why timing constraints must exist before synthesis.
• Production-grade debug workflow: provides a stepwise approach from QoR checks through critical-path fixes (pipeline, pre-registration, retiming, adder restructuring) and GLS readiness (reset coverage, initial-block hazards, X-propagation).

Use case: You run Vivado or Design Compiler and see timing failures (WNS < 0) plus gate-level sim mismatches due to Xs after reset—use this Skill to bring the RTL into a synthesisable form, ensure constraints are applied early, and make the design netlist-ready for GLS.

Quick Start

Use the synthesis-guidelines skill to validate your RTL coding style, apply the right synthesis attributes and SDC prerequisites, then iterate on QoR and GLS readiness until timing closes and reset/X-propagation issues are eliminated.