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KishoreDamam
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synthesis-guidelines

Guide RTL authors in preparing synthesizable SystemVerilog for Vivado and Synopsys DC/Genus.

1|1|Updated Jan 29, 2026
Search Tags:#vivado#timing closure#design compiler#RTL synthesis#gate-level simulation#reset coverage#X-propagation
One-click install
npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill synthesis-guidelines
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: synthesis-guidelines
Source: https://github.com/KishoreDamam/VLSI-agkit/tree/main/.agent/skills/synthesis-guidelines
Command: npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill synthesis-guidelines

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

This Skill helps you avoid RTL patterns and synthesis setup mistakes that cause failed synthesis, poor QoR, timing violations, and gate-level simulation surprises.

Core Features & Use Cases

  • Synthesis-friendly RTL checklist: enforces correct sequential/combinational coding (always_ff/always_comb defaults), avoids latch and combinational-loop inference, and prevents sim-vs-synth mismatches.
  • Pragmatic attribute and constraint guidance: shows how to apply synthesis attributes/directives (Vivado and DC/Genus equivalents) and why timing constraints must exist before synthesis.
  • Production-grade debug workflow: provides a stepwise approach from QoR checks through critical-path fixes (pipeline, pre-registration, retiming, adder restructuring) and GLS readiness (reset coverage, initial-block hazards, X-propagation).

Use case: You run Vivado or Design Compiler and see timing failures (WNS < 0) plus gate-level sim mismatches due to Xs after reset—use this Skill to bring the RTL into a synthesisable form, ensure constraints are applied early, and make the design netlist-ready for GLS.

Quick Start

Use the synthesis-guidelines skill to validate your RTL coding style, apply the right synthesis attributes and SDC prerequisites, then iterate on QoR and GLS readiness until timing closes and reset/X-propagation issues are eliminated.

Frequently Asked Questions about synthesis-guidelines

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I fix RTL synthesis timing closure failures in Vivado or Design Compiler?▼

Fix timing closure by enforcing synthesis-friendly RTL patterns like always_ff/always_comb, applying tool-specific synthesis attributes, ensuring SDC constraints exist before synthesis, and iterating on QoR checks through critical-path fixes like pipelining and retiming.

Why does my gate-level simulation show X-propagation failures after reset?▼

Gate-level simulation X-propagation failures occur when RTL lacks explicit reset coverage or retains initial-block hazards. Resolve this by removing initial blocks, ensuring proper reset coverage, and validating the netlist is GLS-ready before running simulations.

How do I prevent latch inference and combinational loops during RTL synthesis?▼

Prevent latch inference and combinational loops by using correct always_ff and always_comb coding patterns with proper default assignments, avoiding incomplete sensitivity lists, and following a synthesis-friendly RTL checklist before running compile_ultra or synth_design.

What's the best way to resolve negative WNS in Vivado or Synopsys DC synthesis reports?▼

Resolve negative WNS by applying synthesis attributes correctly, verifying SDC constraints are applied early, then iterating on critical-path fixes including pipeline insertion, pre-registration, retiming, and adder restructuring to improve QoR.

Do I need SDC constraints before running RTL synthesis in Vivado or Design Compiler?▼

Yes, SDC constraints must exist before synthesis to ensure accurate timing analysis and QoR evaluation. Applying timing constraints early prevents false critical-path identification and ensures synthesis attributes optimize the correct logic paths.

How do I eliminate simulation versus synthesis mismatches in SystemVerilog RTL?▼

Eliminate sim-vs-synth mismatches by enforcing correct sequential and combinational coding patterns, removing initial-block hazards, ensuring explicit reset coverage, and applying tool-specific synthesis attributes for Vivado and Synopsys DC/Genus equivalence.

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