systemverilog

What problem does it solve?

Inconsistent SystemVerilog style and tool-incompatible patterns cause lint failures, synthesis issues, fragile clock/reset naming, and unreadable RTL that hinders reviews and automation. This Skill centralizes project-specific overrides, enforces naming, declaration order, and synthesizable constructs so generated or modified .sv/.v files are lint- and synthesis-ready.

Core Features & Use Cases

• Naming and Style Enforcement: Enforces port prefixes, snake_case or ALL_CAPS identifiers, no CamelCase, parameter and localparam conventions, and instance/file naming rules.
• Synthesis and Lint Compatibility: Requires logic-only signals, always_ff/always_comb usage, default cases, no magic numbers, and iverilog/VCS compatibility restrictions.
• Declaration Order & Module Structure: Validates mandatory declaration ordering, one-module-per-file rule, and package-based shared types.
• Context-Specific Patterns: Provides power optimization, memory wrapper selection, FPGA considerations, and pipelining guidance for timing closure.
• Use Cases: Run before rtl-lint-check or rtl-synth-check, apply when auto-generating modules or testbenches, and consult when agents perform RTL modifications or create new packages.

Quick Start

Ask the systemverilog skill to validate and enforce project naming, declaration order, and synthesis-safe constructs on generated .sv files.