Enforce SystemVerilog coding conventions on generated and modified RTL files.
npx skills add https://github.com/babyworm/rtl-agent-team --skill systemverilog
Please help me install this Agent Skill. Skill: systemverilog Source: https://github.com/babyworm/rtl-agent-team/tree/main/skills/systemverilog Command: npx skills add https://github.com/babyworm/rtl-agent-team --skill systemverilog
Inconsistent SystemVerilog style and tool-incompatible patterns cause lint failures, synthesis issues, fragile clock/reset naming, and unreadable RTL that hinders reviews and automation. This Skill centralizes project-specific overrides, enforces naming, declaration order, and synthesizable constructs so generated or modified .sv/.v files are lint- and synthesis-ready.
Ask the systemverilog skill to validate and enforce project naming, declaration order, and synthesis-safe constructs on generated .sv files.
High-intent search queries and answers about installing and using this skill.
To enforce consistent SystemVerilog RTL coding conventions, apply rules for port prefixes, snake_case identifiers, declaration order, and always_ff/always_comb usage to ensure generated .sv files are synthesis- and lint-ready.
Required SystemVerilog naming conventions include using port prefixes, snake_case or ALL_CAPS identifiers, avoiding CamelCase, and matching filenames to module names to satisfy VCS and iverilog simulator compatibility restrictions.
To validate SystemVerilog module structure, enforce a mandatory declaration order, apply the one-module-per-file rule, and use package-based shared types to maintain consistent RTL hierarchy across generated files.
Yes, this approach supports power optimization and timing closure by providing context-specific patterns for memory wrapper selection, FPGA considerations, and pipelining guidance during RTL implementation.
Run SystemVerilog convention checks before rtl-lint-check or rtl-synth-check, and apply them when auto-generating modules or testbenches, or when agents perform RTL modifications and create new packages.
Generated SystemVerilog files fail lint checks due to missing default cases, magic numbers, or non-synthesizable constructs; enforcing logic-only signals and standard always_ff/always_comb blocks resolves these synthesis issues.
codejunkie99Guide SystemVerilog RTL design with modern conventions and synthesizable patterns.
amoslee2026Lint HDL sources with Verible and output a JSON report.
babywormEnforce Tier 2 unit testing policy for SystemVerilog testbenches with coverage and escalation rules.
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