systemverilog-assertion

What problem does it solve?

Provides authoritative SVA coding standards and formal verification guidance so assertion authors produce readable, provable, and simulation-compatible checks that reduce false failures and speed debugging.

Core Features & Use Cases

• Naming & Labels: Consistent prefixes for assert/assume/cover and clear property/sequence naming to improve traceability.
• Clock/Reset Guards: default clocking and disable-if patterns plus past_valid guards to avoid spurious failures across reset.
• Bind-File & Tool Integration: Prefer bind-file checkers, include failure messages on all asserts, and follow sv2v guidance for SymbiYosys workflows.
• Use Case: Generate bind-file assertions for AXI or FIFO RTL, verify with SymbiYosys BMC or prove modes, and analyze counterexamples for RTL fixes.

Quick Start

Generate a bind-file SVA checker for a module that uses default clocking, disable iff, labeled asserts with failure messages, and sv2v guidance for SymbiYosys.