skills.rest
KishoreDamam
KishoreDamamCOMMUNITY
Explore all skills by this author →
WebsiteGitHub

systemverilog-coding

Guide SystemVerilog RTL coding patterns for logic types, always_ff/always_comb, interfaces, and generate-for pipelines.

1|1|Updated Jan 29, 2026
Search Tags:#interfaces#rtl#systemverilog#always_ff#always_comb#modports#generate-for
One-click install
npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill systemverilog-coding
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: systemverilog-coding
Source: https://github.com/KishoreDamam/VLSI-agkit/tree/main/.agent/skills/systemverilog-coding
Command: npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill systemverilog-coding

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

This skill prevents common SystemVerilog RTL mistakes by teaching canonical patterns for types, procedural blocks, interfaces, single-driver struct semantics, and parameterized generate pipelines.

Core Features & Use Cases

  • Use correct RTL primitives: choose logic-first declarations and pair them with always_ff/always_comb to avoid subtle simulation/synthesis bugs.
  • Build clean, reusable interfaces: define parameterized interfaces with valid/ready modports for producer/consumer connectivity.
  • Eliminate “multiple drivers” struct errors: drive packed structs safely (whole-struct assignment or split variables) to satisfy single-driver rules.
  • Parameterize pipelines safely: generate N-stage modules with labeled generate-for, plus parameter validation using $fatal.

Example: You are implementing a pipelined, valid/ready RTL block and hit a “multiple drivers on struct field” error or mismatched behavior due to an incorrect combinational block style; apply the skill’s patterns to correct both the code structure and the procedural semantics.

Quick Start

Use systemverilog-coding to generate a SystemVerilog rewrite of your module using logic types, always_ff/always_comb, a parameterized interface with modports, and a generate-for pipelined structure while avoiding multiple-driver and latch/sensitivity issues.

Frequently Asked Questions about systemverilog-coding

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I fix multiple drivers on a packed struct in SystemVerilog RTL?▼

Fix multiple drivers on a packed struct in SystemVerilog RTL by applying single-driver rules, using whole-struct assignment or splitting variables to satisfy synthesis constraints. This prevents latent simulation and synthesis bugs.

When should I use always_ff and always_comb blocks in SystemVerilog?▼

Use always_ff for sequential logic and always_comb for combinational logic in SystemVerilog to enforce tool-checked block semantics. Pairing these with logic-first declarations avoids subtle simulation and synthesis mismatches.

How do I parameterize a generate-for pipeline with valid/ready interfaces in SystemVerilog?▼

Parameterize a generate-for pipeline in SystemVerilog by labeling generate blocks and defining interfaces with valid/ready modports. Validate stage count parameters using elaboration-time $fatal to prevent latent bugs.

What is the correct way to define modports for SystemVerilog interfaces?▼

Define modports for SystemVerilog interfaces by specifying producer and consumer connectivity directions for valid and ready signals. This creates clean, reusable interface plumbing for RTL design and verification.

Why does my SystemVerilog combinational logic infer a latch?▼

Combinational logic infers a latch when using incorrect procedural block styles instead of always_comb. Applying canonical always_comb patterns enforces tool-checked sensitivity lists and prevents unintended latch generation.

Can I use packed structs with single-driver behavior in SystemVerilog RTL?▼

Use packed structs with single-driver behavior in SystemVerilog RTL by ensuring whole-struct assignment or splitting struct fields into separate variables. This satisfies the single-driver rules for logic types during synthesis.

Related Skills

Explore More Software Engineering Skills→
londeylondey
18

claude-skill-verilog

Enforce consistent Verilog and SystemVerilog coding style for Verilator linting and Yosys synthesis.

Community
Intermediate
codejunkie99codejunkie99
3

SystemVerilog RTL Design

Provide SystemVerilog RTL design patterns and templates for synthesizable hardware coding.

Community
Intermediate
RedClausRedClaus

tb-best-practices

Guide SystemVerilog testbench design with layered architectures and verification methodologies.

Community
Advanced
EriemonEriemon
214

erie-verilog-generator

Generate and validate synthesizable Verilog-2001 RTL from hardware requirements.

Community
Advanced