triton-ascend-case-reduction-amax-large

What problem does it solve?

Reduces the bottleneck of large-axis reductions by mapping the reduce axis to multiple cores and performing atomic reductions across thread blocks, avoiding common UB issues in extreme configurations.

Core Features & Use Cases

• Maps the reduce axis to multi-core execution to improve throughput on large N.
• Uses atomic operations for intra-kernel reductions and two-stage tiling to maximize occupancy.
• Suitable for extreme shape ratios like M<<N (e.g., 16×262144) on Ascend hardware.

Quick Start

Run the Triton Ascend case with the provided grid and atomic-min reduction strategy to verify performance on large-scale reductions.