skills.rest
KishoreDamam
KishoreDamamCOMMUNITY
Explore all skills by this author →
WebsiteGitHub

uvm-coding

Implement UVM 1.2 SystemVerilog testbench coding patterns for sequences, drivers, and scoreboards.

1|1|Updated Jan 29, 2026
Search Tags:#constraints#phasing#systemverilog#uvm#scoreboard#tlm#testbench architecture
One-click install
npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill uvm-coding
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: uvm-coding
Source: https://github.com/KishoreDamam/VLSI-agkit/tree/main/.agent/skills/uvm-coding
Command: npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill uvm-coding

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

This Skill prevents common UVM testbench mistakes by standardizing the core coding patterns you use to create sequences, drivers, monitors, scoreboards, and phase/objection behavior for SystemVerilog simulations.

Core Features & Use Cases

  • Sequence item + constraint workflow: design transactions with uvm_object_utils, implement convert2string(), and ensure randomized fields always satisfy constraints.
  • Correct macro usage and driver/monitor handshake: apply uvm_do_with-style constrained stimulus safely and implement the get_next_item / drive / item_done() pattern so sequences never stall.
  • TLM topology for checking and debug: wire monitor output to scoreboards using analysis ports and dual uvm_tlm_analysis_fifo buffers to decouple producer/consumer rates.
  • Phase placement and objection correctness: decide what belongs in build_phase vs run_phase, and use objections so time-consuming stimulus doesn’t end prematurely.

Quick Start

Use the uvm-coding skill to review or implement a UVM testbench structure for a new bus agent, ensuring your sequences, TLM connections, scoreboard compare loop, and run-phase objections follow production-grade best practices.

Frequently Asked Questions about uvm-coding

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I prevent UVM sequences from stalling during SystemVerilog simulation?▼

Prevent UVM sequences from stalling by implementing the correct get_next_item, drive, and item_done driver handshake pattern so sequence execution never blocks waiting for item_done.

What is the correct way to wire UVM TLM analysis ports to a scoreboard?▼

Wiring UVM TLM analysis ports to a scoreboard requires using dual uvm_tlm_analysis_fifo buffers to decouple producer and consumer rates for reliable transaction checking.

How do I use run_phase objections correctly in a UVM testbench?▼

Use run_phase objections in a UVM testbench to prevent time-consuming constrained-random stimulus from ending prematurely before all sequences finish driving transactions.

Why does my UVM scoreboard miss transactions when the monitor rate fluctuates?▼

Your UVM scoreboard misses transactions when monitor rates fluctuate because lacking dual uvm_tlm_analysis_fifo buffers causes a direct coupling bottleneck between producer and consumer.

Can I use uvm_do_with for constrained-random stimulus in a SystemVerilog testbench?▼

Yes, you can use uvm_do_with to apply constrained stimulus safely in a SystemVerilog testbench by ensuring randomized fields always satisfy transaction constraints.

Related Skills

Explore More Software Engineering Skills→
nikolaj-latnikolaj-lat
14

traits

Define and validate character trait definitions with typed schemas and cross-references.

Community
Advanced
babywormbabyworm
43

rtl-p5s-uvm-verify

Run UVM-based verification on RTL with commercial simulators and merge coverage artifacts.

Community
Advanced
chuanseng-ngchuanseng-ng
180

functional-verification

Automate UVM-based functional verification workflows for digital chip designs.

Community
Advanced
rajivhasija79-bitrajivhasija79-bit
3

dv-sequences

Generate UVM sequences, virtual sequences, and test classes from a DV testplan.

Community
Advanced