uvm-coding

What problem does it solve?

This Skill prevents common UVM testbench mistakes by standardizing the core coding patterns you use to create sequences, drivers, monitors, scoreboards, and phase/objection behavior for SystemVerilog simulations.

Core Features & Use Cases

• Sequence item + constraint workflow: design transactions with uvm_object_utils, implement convert2string(), and ensure randomized fields always satisfy constraints.
• Correct macro usage and driver/monitor handshake: apply uvm_do_with-style constrained stimulus safely and implement the get_next_item / drive / item_done() pattern so sequences never stall.
• TLM topology for checking and debug: wire monitor output to scoreboards using analysis ports and dual uvm_tlm_analysis_fifo buffers to decouple producer/consumer rates.
• Phase placement and objection correctness: decide what belongs in build_phase vs run_phase, and use objections so time-consuming stimulus doesn’t end prematurely.

Quick Start

Use the uvm-coding skill to review or implement a UVM testbench structure for a new bus agent, ensuring your sequences, TLM connections, scoreboard compare loop, and run-phase objections follow production-grade best practices.