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verilog-design-skill

Analyze Verilog/FPGA code for correctness issues and optimization suggestions.

21|Updated Apr 16, 2026
Search Tags:#code review#pipeline design#fpga#verilog#resource mapping#timing optimization#reset strategy
One-click install
npx skills add https://github.com/Zhujian-Liang/verilog-design-skill --skill verilog-design-skill
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: verilog-design-skill
Source: https://github.com/Zhujian-Liang/verilog-design-skill/tree/main
Command: npx skills add https://github.com/Zhujian-Liang/verilog-design-skill --skill verilog-design-skill

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

This Skill helps hardware engineers write, review, and debug Verilog/FPGA designs by enforcing practical coding rules and delivering optimization guidance that is tied back to the repository’s references.

Core Features & Use Cases

  • Source-backed Verilog/FPGA guidance: Produces design recommendations, error checks, and code patterns aligned with the included engineering notes.
  • FPGA resource and timing optimization: Covers DSP/BRAM inference constraints, control-set optimization, division avoidance, and multiplication/shift strategies.
  • Pipeline and design-pattern support: Provides latency alignment, sync signal delay techniques, and common image-processing pipeline patterns (e.g., Sobel, 3x3 window generation).
  • Design review & correction workflow: Offers a structured checklist for typical Verilog pitfalls (assignment mixing, missing sensitivity lists, negative feedback combinational loops, reset misuse).

Quick Start

Use the verilog-design-skill to review a Verilog module you provide and ask for a corrected version plus the specific rule(s) violated, with references to the relevant sections.

Frequently Asked Questions about verilog-design-skill

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I fix blocking and non-blocking assignment mixing in Verilog always blocks?▼

To fix Verilog assignment mixing, separate blocking assignments for combinational logic and non-blocking assignments for sequential logic, never mixing them in the same always block. This Skill identifies these violations and provides source-backed corrections.

What is the best way to optimize FPGA timing and resource usage for DSP and BRAM?▼

FPGA timing and resource optimization requires applying correct reset strategies for BRAM/DSP inference and replacing division with shifts or multiply optimizations. This Skill analyzes your design to deliver implementation-friendly arithmetic and resource mapping suggestions.

How do I design a Verilog pipeline with correct latency alignment?▼

Designing a Verilog pipeline with correct latency alignment involves applying sync signal delay techniques and matching data flow stages. This Skill provides pipeline design patterns and verifies latency alignment for modules like image processing windows.

Can I use this to review existing Verilog modules for combinational negative feedback loops?▼

Yes, you can review existing Verilog modules to detect combinational negative feedback loops and missing sensitivity lists. This Skill applies a structured design review checklist to identify typical pitfalls and outputs a corrected version of your logic.

Why does my FPGA implementation fail when using resets on DSP or BRAM blocks?▼

FPGA implementations fail with DSP or BRAM resets because specific reset strategy constraints must be followed to allow proper resource inference. This Skill checks your reset misuse against coding rules and suggests source-backed fixes for resource mapping.

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