verilog-design-skill

What problem does it solve?

This Skill helps hardware engineers write, review, and debug Verilog/FPGA designs by enforcing practical coding rules and delivering optimization guidance that is tied back to the repository’s references.

Core Features & Use Cases

• Source-backed Verilog/FPGA guidance: Produces design recommendations, error checks, and code patterns aligned with the included engineering notes.
• FPGA resource and timing optimization: Covers DSP/BRAM inference constraints, control-set optimization, division avoidance, and multiplication/shift strategies.
• Pipeline and design-pattern support: Provides latency alignment, sync signal delay techniques, and common image-processing pipeline patterns (e.g., Sobel, 3x3 window generation).
• Design review & correction workflow: Offers a structured checklist for typical Verilog pitfalls (assignment mixing, missing sensitivity lists, negative feedback combinational loops, reset misuse).

Quick Start

Use the verilog-design-skill to review a Verilog module you provide and ask for a corrected version plus the specific rule(s) violated, with references to the relevant sections.