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vivado-constraints

Guide Vivado XDC/SDC timing and physical constraint creation for FPGA designs.

156|19|Updated Mar 27, 2026
Search Tags:#constraints#timing#clock#vivado#sdc#xdc
One-click install
npx skills add https://github.com/Shinei-Nouzen-Arch/FPGA-Agent-skills --skill vivado-constraints
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: vivado-constraints
Source: https://github.com/Shinei-Nouzen-Arch/FPGA-Agent-skills/tree/main/vivado-constraints
Command: npx skills add https://github.com/Shinei-Nouzen-Arch/FPGA-Agent-skills --skill vivado-constraints

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This skill helps hardware designers craft Vivado XDC/SDC timing and physical constraints accurately, reducing debugging time and preventing timing violations.

Core Features & Use Cases

  • Support for clock definitions (create_clock, create_generated_clock, virtual clocks) and proper usage across synthesis and implementation.
  • IO timing and delay constraints (set_input_delay, set_output_delay, DDR timing) to ensure reliable data capture.
  • Timing exceptions and CDC controls (set_false_path, set_multicycle_path, set_max_delay, set_min_delay, set_clock_groups, set_bus_skew) to manage cross-domain paths.
  • Constraint scoping, precedence rules, and debugging guidance (SCOPED_TO_REF, constraint ordering, check_timing, report_exceptions, report_clock_interaction).

Quick Start

Start by defining a primary clock on an input port, apply input/output delay constraints, and then add timing exceptions as required for your design.

Frequently Asked Questions about vivado-constraints

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I write Vivado XDC constraints for clocks and IO delays?▼

Vivado XDC constraints for clocks use create_clock and create_generated_clock, while IO delays use set_input_delay and set_output_delay to ensure reliable data capture across synthesis and implementation.

What is the best way to constrain cross-domain paths in Vivado?▼

Cross-domain paths in Vivado are constrained using timing exceptions like set_false_path, set_max_delay, and set_clock_groups to manage CDC interactions and prevent timing violations.

How do I debug timing exceptions and constraint precedence in Vivado?▼

Debug Vivado timing exceptions by checking constraint scoping, ordering, and using report_exceptions and report_clock_interaction to validate precedence rules and identify conflicts.

When do I need virtual clocks for DDR timing in FPGA designs?▼

Virtual clocks are needed for DDR timing in FPGA designs to properly reference set_input_delay and set_output_delay constraints, ensuring accurate data capture and reliable interface timing.

Can I scope XDC constraints to specific modules in non-project mode?▼

XDC constraints can be scoped to specific modules using SCOPED_TO_REF, allowing precise constraint application and precedence control across both project and non-project Vivado contexts.

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