vivado-flow

What problem does it solve?

This Skill removes the frustration of non-reproducible FPGA build steps by guiding you to run a complete Xilinx Vivado flow from Tcl, including synthesis, implementation, and optional ILA/VIO debug setup.

Core Features & Use Cases

• Reproducible Vivado Tcl builds: Stand up a project, run synth_design/opt_design/place_design/route_design, and generate a bitstream without relying on GUI actions.
• Inference-ready RTL patterns: Encourage BRAM/DSP48/FIFO inference using clean SystemVerilog or Tcl IP configuration rather than fragile primitives.
• In-system debug integration: Insert ILA/VIO cores and mark nets for observation to accelerate bring-up and troubleshooting.
• Resource optimization tactics: Apply practical fit-focused techniques (BRAM/DSP usage, pipelining, floorplanning guidance) when implementation struggles.

Use case: You need a CI-friendly build that turns an RTL + XDC constraint set into a bitstream and, on demand, adds ILA probes to a specific data bus for post-silicon debugging.

Quick Start

Ask the AI to produce a Vivado Tcl script that reads your RTL sources and XDC constraints, runs synth_design through write_bitstream, and optionally inserts an ILA core probing your data[*] nets while ensuring BRAM/DSP inference patterns are consistent with your RTL.