Write a Backend-Agnostic Kernel Plan

What problem does it solve?

This skill guides engineers and AI coding agents to plan compute kernels that must run correctly and performantly across multiple hardware backends (NVIDIA, AMD, CPU, and emerging targets) before writing any backend-specific implementation. It prevents common portability mistakes such as assuming a 32-thread warp, hardcoding tile shapes, or skipping a CI strategy for secondary vendors.

Core Features & Use Cases

• Cross-backend abstraction selection: Evaluate Triton, HIP single-source, backend dispatch, and framework operator approaches and choose the best fit for the operation and team constraints.
• Hardware feature mapping and risk register: Identify backend feature gaps (tensor cores, FP8, warp/wavefront width) and produce mitigations and fallbacks.
• Portability primitives and tile strategies: Specify a thin portability header (warp/wavefront macros), per-backend tile recommendations, and runtime/configurable tuning knobs.
• CI and correctness planning: Define a CI matrix covering multiple SM/wavefront generations and a CPU fallback for correctness validation.
• Use case: Planning a GEMM-like or attention kernel that must ship on NVIDIA A100/H100 and AMD MI300X while retaining a CPU fallback for small shapes.

Quick Start

Create a backend-agnostic kernel plan for an attention-like operation targeting NVIDIA A100 and AMD MI300X that lists the chosen abstraction, portability header primitives, per-backend tile sizes, a portability risk register, and the CI matrix.