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Write a Backend-Agnostic Kernel Plan

Plan backend-agnostic compute kernels for NVIDIA, AMD, and CPU targets.

54|7|Updated Apr 10, 2026
Search Tags:#performance#gpu#kernel#portability#cuda#triton#rocm
One-click install
npx skills add https://github.com/KrxGu/kernel-skills --skill write-a-backend-agnostic-kernel-plan
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: Write a Backend-Agnostic Kernel Plan
Source: https://github.com/KrxGu/kernel-skills/tree/main/skills/portability/write-backend-agnostic-kernel-plan
Command: npx skills add https://github.com/KrxGu/kernel-skills --skill write-a-backend-agnostic-kernel-plan

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This skill guides engineers and AI coding agents to plan compute kernels that must run correctly and performantly across multiple hardware backends (NVIDIA, AMD, CPU, and emerging targets) before writing any backend-specific implementation. It prevents common portability mistakes such as assuming a 32-thread warp, hardcoding tile shapes, or skipping a CI strategy for secondary vendors.

Core Features & Use Cases

  • Cross-backend abstraction selection: Evaluate Triton, HIP single-source, backend dispatch, and framework operator approaches and choose the best fit for the operation and team constraints.
  • Hardware feature mapping and risk register: Identify backend feature gaps (tensor cores, FP8, warp/wavefront width) and produce mitigations and fallbacks.
  • Portability primitives and tile strategies: Specify a thin portability header (warp/wavefront macros), per-backend tile recommendations, and runtime/configurable tuning knobs.
  • CI and correctness planning: Define a CI matrix covering multiple SM/wavefront generations and a CPU fallback for correctness validation.
  • Use case: Planning a GEMM-like or attention kernel that must ship on NVIDIA A100/H100 and AMD MI300X while retaining a CPU fallback for small shapes.

Quick Start

Create a backend-agnostic kernel plan for an attention-like operation targeting NVIDIA A100 and AMD MI300X that lists the chosen abstraction, portability header primitives, per-backend tile sizes, a portability risk register, and the CI matrix.

Frequently Asked Questions about Write a Backend-Agnostic Kernel Plan

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I plan a backend-agnostic compute kernel for NVIDIA and AMD GPUs?▼

Planning a backend-agnostic compute kernel involves defining cross-backend abstraction boundaries, portability primitives for warp/wavefront handling, and per-backend tile strategies before writing implementation code for NVIDIA, AMD, and CPU targets.

What is the best way to handle warp and wavefront differences in portable GPU kernels?▼

Handling warp and wavefront differences in portable GPU kernels requires specifying a thin portability header with macros to map 32-thread warps to 64-thread wavefronts, ensuring correct execution across NVIDIA and AMD hardware targets.

How do I choose between Triton and HIP single-source for cross-backend kernel portability?▼

Choosing between Triton and HIP single-source for cross-backend kernel portability involves evaluating operation constraints, team expertise, and backend feature gaps to select the best cross-backend abstraction for your specific GEMM-like or attention operations.

Does writing portable Triton kernels require a CI matrix for multiple SM generations?▼

Yes, writing portable Triton kernels requires a CI matrix covering multiple SM/wavefront generations and a CPU fallback to validate correctness and prevent portability mistakes across secondary vendors like AMD.

How to mitigate tensor core and FP8 feature gaps when targeting AMD MI300X and NVIDIA H100?▼

Mitigating tensor core and FP8 feature gaps when targeting AMD MI300X and NVIDIA H100 requires creating a hardware feature risk register that identifies backend limitations and produces specific fallbacks and mitigations.

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