Tensormux
Official@tensormux
Making Inference Great Again.
Agent Skills by Tensormux
Showing 10 vetted skills indexed across 1 GitHub repositories.
tensormuxChoose Tile Size and Work Partitioning
Determine tile sizes and grid layouts for CUDA or Triton kernels.
tensormuxWrite CUDA LayerNorm Kernel
Write CUDA LayerNorm kernels with Welford reduction and FP32 accumulation.
tensormuxChoose CUDA Launch Configuration
Determine optimal CUDA launch configurations by analyzing resource usage and hardware limits.
tensormuxAvoid Warp Divergence
Classify warp divergence in CUDA kernels and estimate cost with Nsight Compute metrics.
tensormuxWrite Triton LayerNorm Kernel
Write a Triton LayerNorm kernel with RMSNorm support and masking.
tensormuxOptimize Triton Block Parameters
Autotune Triton GEMM block sizes and launch parameters for GPU throughput.
tensormuxWrite an FP8 Kernel
Design FP8 compute kernels with E4M3/E5M2 scaling for NVIDIA Hopper and Ada GPUs.
tensormuxPort CUDA Kernel to HIP
Port CUDA kernels to HIP for ROCm-enabled AMD GPUs.
tensormuxWrite a Triton RMSNorm Kernel
Implement a numerically stable RMSNorm kernel in Triton with fp32 accumulation.
tensormuxWrite a Triton Dequant Kernel (int4 / int8 → fp16 / bf16)
Implements Triton dequantization of int4/int8 weights to fp16/bf16 with AWQ/GPTQ/NF4 support.
Frequently Asked Questions About Tensormux
FAQPage SchemaWhat specific GPU performance tasks does Tensormux enable?▼
Tensormux enables the design and optimization of high-performance compute kernels, including LayerNorm, RMSNorm, and FP8 scaling. It provides technical guidance for configuring CUDA launch parameters, managing warp divergence, and autotuning Triton block sizes to maximize throughput on NVIDIA and AMD hardware.
Which engineering personas benefit from these GPU kernel skills?▼
These skills are designed for systems engineers, machine learning infrastructure developers, and hardware acceleration specialists. Professionals tasked with reducing inference latency, optimizing memory bandwidth, or porting compute-heavy workloads across heterogeneous GPU architectures will find these technical capabilities directly applicable to their development cycles.
What are the hardware and software prerequisites for implementing these kernels?▼
Implementation requires a development environment configured with the NVIDIA CUDA Toolkit or the Triton compiler stack. For cross-platform support, an AMD ROCm installation is necessary. Developers should have access to Nsight Compute for profiling warp divergence and resource usage metrics to validate kernel performance improvements.