Port CUDA Kernel to HIP

Port CUDA kernels to HIP for ROCm-enabled AMD GPUs.

54|7|Updated Apr 10, 2026
One-click install
npx skills add https://github.com/tensormux/kernel-skills --skill port-cuda-kernel-to-hip
Or copy as Structured Prompt for Agent
Please help me install this Agent Skill.
Skill: Port CUDA Kernel to HIP
Source: https://github.com/tensormux/kernel-skills/tree/main/skills/portability/port-cuda-kernel-to-hip
Command: npx skills add https://github.com/tensormux/kernel-skills --skill port-cuda-kernel-to-hip

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Port CUDA kernels to HIP for ROCm-enabled AMD GPUs while preserving correctness and performance intent during migration.

Core Features & Use Cases

  • HIP porting workflow: From CUDA to HIP using hipify, with careful review of semantic differences.
  • Wavefront and memory model adaptation: Handles AMD's 64-wide wavefronts and memory semantics.
  • Validation & tooling guidance: Guidance on compiling, testing, and verifying numerical equivalence to the CUDA reference.

Quick Start

Port a minimal CUDA kernel to HIP and verify functional parity on an AMD device.

Frequently Asked Questions about Port CUDA Kernel to HIP

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I port CUDA kernels to HIP for AMD ROCm hardware?

Port CUDA kernels to HIP using hipify for initial API mapping, then apply manual fixes for wavefront width differences and memory model adaptations to maintain performance intent on AMD ROCm devices.

What is the difference between CUDA warps and AMD HIP wavefronts during migration?

AMD HIP uses 64-wide wavefronts compared to CUDA's 32-wide warps. HIP porting requires adapting kernel indexing and synchronization logic to handle this wavefront width difference correctly.

Can I use hipify to automatically convert an entire CUDA codebase to HIP?

Hipify provides initial CUDA to HIP API mappings, but manual fixes are required across the codebase to handle semantic differences, memory model adaptations, and wavefront width differences.

How do I validate HIP kernel correctness against the original CUDA reference?

Validate HIP kernel correctness by compiling, testing, and verifying numerical equivalence against the CUDA reference output on an AMD device to ensure functional parity after migration.

Does porting CUDA to HIP require adapting memory model semantics?

Porting CUDA to HIP requires memory model adaptations to handle semantic differences between NVIDIA and AMD hardware, ensuring correct memory access patterns and performance intent preservation.