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EriemonEriemonCommunity·1 Agent Skills Included

verilog-generator

Generate, review, and repair readable Verilog-2001 RTL

Generates synthesizable Verilog-2001 RTL modules from plain design requirements, with spec documents and WaveDrom timing previews. Reviews existing RTL for reset, handshake, width, naming, and synthesis risks, and repairs designs from real compiler or simulator logs. Adds semantic comments without changing logic and runs strict quality gates so unverified checks are never reported as passed.
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npx skills add Eriemon/verilog-generator --all -g -y

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EriemonEriemon

erie-verilog-generator

Generate and validate synthesizable Verilog-2001 RTL from hardware requirements.

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Frequently Asked Questions

FAQPage Schema
How to install Verilog Generator?▼

Run `npx skills add Eriemon/verilog-generator --all -g -y` in your terminal to install the skill globally. After installation, call it with `$readable-verilog-generator` or describe your Verilog task directly.

How to generate Verilog RTL from a text requirement?▼

Describe the module's purpose, ports, clock and reset behavior, and timing rules. The skill shows a spec and WaveDrom behavior preview for your confirmation before writing the final synthesizable Verilog-2001 code.

Can it review or fix my existing Verilog code?▼

Yes. It performs read-only reviews of reset behavior, handshakes, widths, and naming, and can repair a design using real compiler, linter, or simulator logs with evidence-backed minimal changes.

Does Verilog Generator work with Claude Code and Codex?▼

Yes. It follows the universal SKILL.md standard and supports Codex, Claude, Gemini, and DeepSeek harnesses out of the box.

Can it run simulations or synthesis checks?▼

It can prepare testbench scaffolds and run Vivado xsim, iverilog, or yosys checks when the tools are available. Results from checks that did not actually run are never reported as passed.

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