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erie-verilog-generator

Generate and validate synthesizable Verilog-2001 RTL from hardware requirements.

214|12|Updated May 8, 2026
Search Tags:#testbench#verilog#hardware design#rtl analysis#rtl generation#verify repair#static lint
One-click install
npx skills add https://github.com/Eriemon/verilog-generator --skill erie-verilog-generator
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: erie-verilog-generator
Source: https://github.com/Eriemon/verilog-generator/tree/main
Command: npx skills add https://github.com/Eriemon/verilog-generator --skill erie-verilog-generator

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes scripts (resource) and references (resource) and assets (resource) components.

What problem does it solve?

This Skill helps hardware engineers turn confirmed design requirements, existing RTL, testbenches, and tool diagnostics into readable, reviewable, and verifiable Verilog-2001 artifacts without overstating unrun validation results.

Core Features & Use Cases

  • RTL Generation: Create synthesizable Verilog-2001 modules and self-checking testbench artifacts from structured requirements.
  • RTL Analysis and Repair: Explain existing modules, identify interface and timing risks, diagnose failures, prepare controlled repair plans, and compare RTL semantics.
  • Quality and Validation: Apply strict formatter-backed readability gates, naming and comment rules, static linting, artifact extraction, workflow tracing, and optional local or remote simulator and synthesis readiness checks.
  • Use Case: Provide an AXI-Stream module specification or a failing Verilog design with its diagnostics to receive a structured implementation or repair workflow with explicit validation evidence.

Quick Start

Ask the Verilog Generator skill to create or analyze a Verilog-2001 RTL module from the provided specification, including its ports, clock and reset behavior, expected timing, and verification cases.

Frequently Asked Questions about erie-verilog-generator

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I generate synthesizable Verilog RTL from hardware design requirements?▼

To generate synthesizable Verilog RTL, provide confirmed hardware requirements including ports, clock and reset behavior, and expected timing. The skill produces readable Verilog-2001 modules and self-checking testbench artifacts through a staged workflow with strict formatter-backed readability gates.

How do I repair failing Verilog RTL using tool diagnostics?▼

Repair failing Verilog RTL by providing the existing design and its tool diagnostics to receive a controlled repair plan. The skill diagnoses failures, identifies interface and timing risks, and applies explicit automation modes for repair with truthful reporting of static validation evidence.

Can I use this to analyze and explain existing Verilog-2001 modules and FSMs?▼

Yes, you can analyze existing Verilog-2001 modules by submitting the RTL for review. The skill explains module logic, reviews interfaces and FSMs, performs semantic comparison, and applies static linting to identify timing risks and quality issues.

What is the best way to create a self-checking testbench for hardware verification?▼

The best way to create a self-checking testbench is to define verification cases alongside your module specification. The skill scaffolds self-checking testbench artifacts from structured requirements, supporting optional local or remote simulation to validate the generated hardware design.

Does Verilog RTL generation support optional local or remote simulation workflows?▼

Verilog RTL generation supports optional local or remote simulator and synthesis readiness checks. It provides implementation readiness workflows and truthfully reports externally executed validation evidence without overstating unrun simulation results for the generated testbench artifacts.

When should I use a staged workflow for Verilog RTL repair and validation?▼

Use a staged workflow for Verilog RTL repair when you need strict formatter-backed artifact gates and explicit automation modes. This approach ensures controlled repair plans, semantic comparison, and truthful reporting of static quality checks rather than unverified validation claims.

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