vivado-sim

Automate Verilog/SystemVerilog simulation workflows using Vivado xsim.

Updated Mar 17, 2026

Search Tags:#simulation #testbench #systemverilog #hdl #vivado #xsim #verilog

Ready to run

npx skills add https://github.com/pjy4617/pjy-claude-skill --skill vivado-sim

💬 Prompt for ChatGPT / Claude Chat▼

Please help me install this Agent Skill.
Skill: vivado-sim
Source: https://github.com/pjy4617/pjy-claude-skill/tree/main/plugins/vivado/skills/vivado-sim
Command: npx skills add https://github.com/pjy4617/pjy-claude-skill --skill vivado-sim

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Verilog and SystemVerilog testbenches often require repetitive, error-prone commands for compilation, elaboration, and simulation. This Skill standardizes the end-to-end Vivado xsim workflow, enabling reliable, repeatable runs with minimal manual setup.

Core Features & Use Cases

CLI-driven simulation: compile with xvlog, elaborate with xelab, and run with xsim in batch mode.
GUI-assisted debugging: switch to GUI for waveform inspection when needed.
Use Case: quickly validate a new RTL module by producing a waveform, a log, and a pass/fail result from a single command sequence.

Quick Start

Execute the full Vivado simulation workflow for a given testbench from compilation to waveform export.

Frequently Asked Questions about vivado-sim

High-intent search queries and answers about installing and using this skill.

FAQPage Schema

How do I automate Verilog simulations with Vivado xsim?▼

Automating Verilog simulations with Vivado xsim involves sequentially running xvlog, xelab, and xsim commands. This removes manual setup and provides a repeatable workflow that outputs simulation logs and pass/fail results.

How do I run a SystemVerilog testbench in batch mode using Vivado?▼

To run a SystemVerilog testbench in batch mode, execute the Vivado xsim toolchain commands: compile with xvlog, elaborate with xelab, and run the simulation with xsim. This CLI-driven approach quickly validates HDL modules without GUI overhead.

What Vivado version is required for xsim simulation automation?▼

Vivado 2020.1 or later is required for xsim simulation automation. The workflow relies on the specific implementations of the xvlog, xelab, and xsim execution steps found in this version or newer releases of the Vivado toolchain.

Can I debug SystemVerilog waveforms in GUI mode after running xsim in batch?▼

Yes, you can switch to GUI-assisted debugging for waveform inspection. While the standard workflow uses CLI batch mode for automated runs, the Skill supports switching to GUI mode to visually analyze and debug HDL waveforms when needed.

Why do I need to run xvlog and xelab before executing xsim?▼

You need to run xvlog and xelab before xsim because Verilog/SystemVerilog simulation requires compiling source files first, then elaborating the design hierarchy, before the simulation can execute and produce waveforms or logs.

Does this Vivado xsim workflow support both Verilog and SystemVerilog HDL files?▼

Yes, the Vivado xsim workflow supports both Verilog and SystemVerilog HDL files. It automates the compilation, elaboration, and simulation steps for testbenches written in either hardware description language to generate waveforms and test results.