vivado-sim

What problem does it solve?

Verilog and SystemVerilog testbenches often require repetitive, error-prone commands for compilation, elaboration, and simulation. This Skill standardizes the end-to-end Vivado xsim workflow, enabling reliable, repeatable runs with minimal manual setup.

Core Features & Use Cases

• CLI-driven simulation: compile with xvlog, elaborate with xelab, and run with xsim in batch mode.
• GUI-assisted debugging: switch to GUI for waveform inspection when needed.
• Use Case: quickly validate a new RTL module by producing a waveform, a log, and a pass/fail result from a single command sequence.

Quick Start

Execute the full Vivado simulation workflow for a given testbench from compilation to waveform export.