Automate Verilog/SystemVerilog simulation workflows using Vivado xsim.
npx skills add https://github.com/pjy4617/pjy-claude-skill --skill vivado-sim
Please help me install this Agent Skill. Skill: vivado-sim Source: https://github.com/pjy4617/pjy-claude-skill/tree/main/plugins/vivado/skills/vivado-sim Command: npx skills add https://github.com/pjy4617/pjy-claude-skill --skill vivado-sim
Verilog and SystemVerilog testbenches often require repetitive, error-prone commands for compilation, elaboration, and simulation. This Skill standardizes the end-to-end Vivado xsim workflow, enabling reliable, repeatable runs with minimal manual setup.
Execute the full Vivado simulation workflow for a given testbench from compilation to waveform export.
High-intent search queries and answers about installing and using this skill.
Automating Verilog simulations with Vivado xsim involves sequentially running xvlog, xelab, and xsim commands. This removes manual setup and provides a repeatable workflow that outputs simulation logs and pass/fail results.
To run a SystemVerilog testbench in batch mode, execute the Vivado xsim toolchain commands: compile with xvlog, elaborate with xelab, and run the simulation with xsim. This CLI-driven approach quickly validates HDL modules without GUI overhead.
Vivado 2020.1 or later is required for xsim simulation automation. The workflow relies on the specific implementations of the xvlog, xelab, and xsim execution steps found in this version or newer releases of the Vivado toolchain.
Yes, you can switch to GUI-assisted debugging for waveform inspection. While the standard workflow uses CLI batch mode for automated runs, the Skill supports switching to GUI mode to visually analyze and debug HDL waveforms when needed.
You need to run xvlog and xelab before xsim because Verilog/SystemVerilog simulation requires compiling source files first, then elaborating the design hierarchy, before the simulation can execute and produce waveforms or logs.
Yes, the Vivado xsim workflow supports both Verilog and SystemVerilog HDL files. It automates the compilation, elaboration, and simulation steps for testbenches written in either hardware description language to generate waveforms and test results.
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