Analyze failed hardware simulation logs to identify root causes.
npx skills add https://github.com/xsw632/ChipAgent --skill debug-xsw632
Please help me install this Agent Skill. Skill: debug Source: https://github.com/xsw632/ChipAgent/tree/main/skills/debug Command: npx skills add https://github.com/xsw632/ChipAgent --skill debug-xsw632
When hardware simulation tests fail, manually cross-referencing simulation logs, design specifications, source code, and waveform data to identify root causes is extremely time-consuming and prone to human error.
Use the debug skill to analyze simulation failures for your hardware module.
High-intent search queries and answers about installing and using this skill.
Debugging failed Verilator simulation tests is automated by cross-referencing simulation logs, Chisel source code, and module specifications to identify root causes and generate actionable fix recommendations.
The root cause of a hardware verification failure in Chisel is found by parsing simulation logs, mapping failures to hardware spec operations, and extracting mismatched signal values from VCD waveform files.
Analyzing VCD waveform files to debug Chisel hardware simulations is supported by extracting signal values at failure timestamps to provide concrete evidence of root causes, with fallback to log-only analysis if waveforms are unavailable.
Module specification files are required to debug FIRRTL compilation and simulation failures, as the analysis matches failed tests to corresponding hardware spec operations to generate structured debug reports.
Your Chisel simulation may fail due to mismatched signal values, and fix suggestions are generated by cross-referencing failed simulation logs with source code to produce structured debug reports with concrete code fixes.
The limitation of hardware debugging without VCD waveform files is the inability to extract signal values at failure timestamps, forcing a fallback to log-only analysis and reducing the precision of root cause identification.
xsw632Run Verilator lint-only checks on generated Verilog for hardware modules.
arbazkhan971Reproduce failing tests and runtime errors to prove root causes with file:line evidence.
babywormGenerate minimal SystemVerilog testbenches and analyze VCD waveforms to isolate RTL failures.
AgainstWarAnalyze Verilog, SystemVerilog, and VHDL failures to produce ranked root-cause hypotheses.
