rtl-bug-repro

What problem does it solve?

Reproducing RTL failures from large regression suites is slow and noisy; this skill creates focused, minimal testbenches and performs waveform analysis so engineers can quickly find the first failing cycle and the originating signal path.

Core Features & Use Cases

• Minimal repro generation: scaffold and write a compact SystemVerilog testbench targeted at the failing module using project naming and clock/reset conventions.
• Waveform comparison and analysis: cycle-by-cycle VCD comparison to identify the first divergence and trace signals to the offending module and context.
• Verification workflow: runs targeted simulations, confirms reproduction, and produces a root_cause.md documenting failure cycle, hierarchical signal trace, and suspected RTL location; useful for regression failures, reported bug isolation, and pre-fix verification.

Quick Start

Use the rtl-bug-repro skill to create a minimal reproduction testbench from a failing simulation log and generate sim/bugs/{bug_id}/root_cause.md with the failure cycle and signal trace.