Hyun-Gyu (Ethan) Kim
Community@babyworm
Agent Skills by Hyun-Gyu (Ethan) Kim
Showing 94 vetted skills indexed across 1 GitHub repositories.
babywormp1-spec-research
Refine ambiguous hardware specifications into validated requirements with acceptance criteria.
babywormrat-init-project
Initialize RTL project workspaces with standardized directories, templates, and EDA scripts.
babywormrtl-ipxact-gen
Generate IEEE 1685-2014 IP-XACT XML descriptors from RTL module definitions.
babywormrtl-p5s-perf-verify
Measure RTL throughput, latency, and stall cycles against BFM baselines.
babywormrtl-p5-verify-team
Orchestrate end-to-end RTL verification workflows across multiple modules with dependency-aware task graphs.
babywormrtl-p5a-functional-closure
Coordinate Phase 5A functional verification closure across RTL modules, blocks, and top-level integration.
babywormrat-p1p3-spec-uarch-policy
Enforce phase-gate policy and governance for the Phase 1→3 RTL design pipeline.
babywormrtl-p5-verify
Orchestrate three-stage Phase 5 RTL verification with lint, formal, CDC, and regression reports.
babywormsyn-tool-profiles
Generate replayable synthesis profiles for yosys, dc_shell, and genus.
babywormrat-p4p5-impl-verify-policy
Enforce Phase 4 to 5 gate criteria before RTL verification.
babywormuvm
Standardize UVM testbench class naming, factory usage, and phase handling.
babywormrtl-p5s-sva-check
Extract SystemVerilog assertions from RTL and run SymbiYosys formal verification.
babywormp1-spec-research-policy
Generates Iron and organic requirements for hardware design projects.
babywormrtl-lint-check
Lints RTL files using Verilator, Verible, slang, and a custom convention checker across rtl/ and sim/ directories.
babywormrtl-p5s-coverage-policy
Analyze RTL coverage reports to prioritize directed test guidance and exclusions.
babywormsystemverilog
Enforce SystemVerilog coding conventions on generated and modified RTL files.
babywormrat-ultraloop
Execute unattended implement-review-improve loops with contract tests and design-freeze enforcement.
babywormlint-tool-profiles
Normalize lint results from Verilator, Verible, slang, and Spyglass into a unified report.
babywormrat-auto-design-policy
Validate RTL design phase artifacts and quality gates across a six-phase pipeline.
babywormrtl-p4-implement-team
Coordinate parallel RTL coding, linting, verification, and integration across a 10-wave pipeline.
babywormrtl-p5s-sva-policy
Define SVA coding conventions and iterative formal verification workflows for RTL designs.
babywormrat-dse
Coordinates Design, Space Exploration across phases with git worktrees and self-critique.
babywormrat-dse-policy
Generate policy-driven design space exploration guidance for RTL architecture choices.
babywormp2-arch-design-policy
Define Phase 2 architecture review criteria and hardware candidate evaluation methodology.