rat-dse-policy

Design space exploration (DSE) for RTL architecture systematically compares algorithms and microarchitecture candidates to make hardware design decisions repeatable and auditable. It enforces quality gates, ADR recording, and bitexact C model transformations.

To enforce quality gates during DSE, apply explicit PASS/FAIL semantics and retry limits for Phase 1→2, Phase 2→3, and Phase 3 completion. This ensures artifact definitions are met before advancing the hardware design workflow.

To transform a functional C model into architectural refc code, restructure it into block-aligned, DPI-C compatible components. The DSE policy mandates bitexact verification to ensure the transformation matches the original functional behavior.

Yes, you can use an automated self-critique protocol with worktree-based trial comparison to iterate and select the best RTL architecture candidate. This workflow evaluates multiple trials quantitatively to produce a defensible pre-implementation package.

The best way to record hardware algorithm comparison rationale is using structured algorithm comparison matrices and Architecture Decision Records (ADRs). This prevents lost rationale and makes DSE choices defensible during Phase 4 review.

You should avoid policy-driven DSE workflows for microarchitecture choices when your project requires rapid, ad-hoc prototyping without auditable decision trails. This structured process enforces strict quality gates and bitexact verification that may hinder fast, exploratory hacking.