Build bitexact C11 reference models for H.264/H.265 codec validation.
npx skills add https://github.com/babyworm/rtl-agent-team --skill ref-model
Please help me install this Agent Skill. Skill: ref-model Source: https://github.com/babyworm/rtl-agent-team/tree/main/skills/ref-model Command: npx skills add https://github.com/babyworm/rtl-agent-team --skill ref-model
Building a reliable, bitexact software oracle for algorithm validation and early bandwidth estimation removes ambiguity between specification and RTL implementation and prevents costly late-stage fixes. The skill ensures that algorithm correctness is proven against industry reference implementations (JM/HM) before hardware development proceeds.
Build a DPI-C compatible C reference model in refc/, run its self-test, and generate conformance_report.json and bandwidth_report.json.
High-intent search queries and answers about installing and using this skill.
Build a bitexact C reference model by creating a DPI-C compatible C11 implementation in refc/, using ext_mem_read/ext_mem_write abstractions to validate algorithm correctness before RTL development.
A bitexact functional reference model serves as a software oracle to validate codec algorithm correctness against JM/HM test vectors, removing ambiguity between specification and RTL implementation to prevent late-stage fixes.
Generate bandwidth analysis reports by tracking external memory accesses through ext_mem_read and ext_mem_write abstractions, running bandwidth sweeps with PARALLEL_LANES variations to produce a bandwidth_report.json.
Yes, you can use a C11 reference model with SystemVerilog DPI-C. The model produces pure C code without clock or reset semantics, making it directly callable from SystemVerilog environments.
Verify codec conformance by running automated bitexact comparisons against JM and HM test vectors. This process generates a conformance_report.json and verifies feature coverage against iron-requirements.json.
babywormGenerate SystemC TLM 2.0 BFMs with LT b_transport and AXI support.
xsw632Automates Verilator simulation runs and structured pass/fail reporting from logs.
babywormEnforce Tier 2 unit testing policy for SystemVerilog testbenches with coverage and escalation rules.
santosomarGenerate test oracles using reference implementations, invariants, and differential comparison.
