rtl-p4s-unit-test-policy

What problem does it solve?

Ensures consistent, repeatable, and auditable Tier 2 unit testing for RTL modules by defining naming conventions, execution modes, result schemas, coverage gates, and escalation rules so teams can reliably validate uarch features and reference-model conformance.

Core Features & Use Cases

• Defines mandatory testbench coding conventions (port prefixes, clock/reset names, instance naming, file naming).
• Specifies execution policy and reference comparison modes (DPI-C or file-based) and the required result JSON schema for tooling integration.
• Enforces mandatory error-injection tests, minimum coverage targets, coverage gap-fill rounds, and escalation rules for unavailable simulators or persistent mismatches.
• Use case: validate per-module SystemVerilog testbenches, run simulations, compare RTL to reference models, produce sim/{module}/{module}_unit_results.json, and escalate failing or ambiguous cases to architects or ref-model developers.

Quick Start

Validate Tier 2 unit tests for module 'my_module' and produce the per-feature unit_results.json with coverage and reference comparison status.