rtl-p4s-unit-test-policy

You can enforce consistent RTL unit testbench policies by validating port prefixes, clock and reset names, instance naming, and mandatory coverage targets to ensure repeatable and auditable SystemVerilog verification runs.

A Tier 2 unit test policy defines per-module SystemVerilog testbench rules, including mandatory error-injection tests, coverage gap-fill rounds, and result JSON schemas to reliably validate microarchitecture features and reference-model conformance.

To compare RTL against a reference model using DPI-C, you execute the specified reference comparison mode, validate DPI-C build artifacts, and output the comparison status into a structured result JSON schema for tooling integration.

Yes, Tier 2 RTL verification supports both DPI-C and file-based reference comparison modes, allowing teams to validate module testbenches and produce sim/{module}/{module}_unit_results.json regardless of the chosen comparison method.

Escalation rules for persistent RTL reference model mismatches involve routing failing or ambiguous module testbench cases to architects or reference-model developers when coverage gap-fill rounds are exhausted or simulators are unavailable.