rtl-p4s-unit-test

Verify RTL modules by generating and running unit testbenches that compare RTL outputs to a C reference model using DPI-C or file-based comparison modes. This detects semantic mismatches in microarchitecture behaviors like FSM transitions and pipeline stages.

Per-module unit testing in RTL simulation produces targeted testbenches that go beyond connectivity smoke tests to validate microarchitecture-level behaviors, exercising FSM transitions, pipeline stages, and data transformations against expected outputs.

Generate a testbench for FSM transitions and pipeline behavior by invoking the unit test orchestrator, which creates sim/{module}/tb_{module}.sv files to automate failure analysis, coverage checks, and regression gating for your RTL.

Yes, you need lint-clean RTL, a passing Tier 1 smoke test, access to the C reference model, and a simulation flow supporting DPI-C or file-based comparison before running unit verification testbenches.

Yes, RTL unit verification supports both DPI-C and file-based comparison modes to compare RTL outputs against the C reference model, accommodating different simulation flow setups and toolchain constraints.

Automate failure analysis for RTL module mismatches by generating sim/{module}/{module}_unit_results.json files during unit testbench execution, which enables rapid triage, coverage checks, and regression gating.