Generates C++ Verilator; testbenches from spec.json files for hardware modules.
npx skills add https://github.com/xsw632/ChipAgent --skill testbench
Please help me install this Agent Skill. Skill: testbench Source: https://github.com/xsw632/ChipAgent/tree/main/skills/testbench Command: npx skills add https://github.com/xsw632/ChipAgent --skill testbench
Manually writing Verilator testbenches for hardware modules is time-consuming and prone to errors, especially when adhering to strict UVM-inspired architecture and Verilator port naming conventions.
Use the testbench skill to generate a complete C++ Verilator testbench for your hardware module that has a pre-generated spec.json file in the workspace.
High-intent search queries and answers about installing and using this skill.
You can generate a Verilator testbench from a spec.json file by using an automated generation skill that reads your structured hardware specifications and directly outputs complete C++ testbench code, eliminating manual boilerplate setup for your simulation runs.
A UVM-inspired testbench architecture for Verilator is a standardized verification structure that includes test cases, drivers, monitors, scoreboards, and reporters to ensure reliable and consistent pass/fail output formatting for hardware module simulations.
You automate boundary and edge case test vector generation by defining your hardware module parameters in a spec.json file, which allows an automated testbench generator to create and apply comprehensive test vectors for your verification workflow.
Yes, you can use automated testbench generation for complex Chisel CPU reference models, as the generation process supports digital hardware verification workflows for modules of any complexity, including simple arithmetic units and full CPU reference models.
Yes, the generated C++ testbench handles correct Verilator io_ port naming automatically, ensuring the test cases, drivers, and monitors interface accurately with the hardware module ports during simulation without manual naming errors.
The limitation of using spec.json for hardware testbench generation is that it requires a pre-generated, structured specification file in the workspace, meaning any unstructured or incomplete hardware definitions cannot be processed for automated Verilator testbench creation.
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