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lint

Run Verilator lint-only checks on generated Verilog for hardware modules.

2|Updated Mar 16, 2026
Search Tags:#simulation#code validation#lint#verilator#verilog#hardware design#chisel
One-click install
npx skills add https://github.com/xsw632/ChipAgent --skill lint-xsw632
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: lint
Source: https://github.com/xsw632/ChipAgent/tree/main/skills/lint
Command: npx skills add https://github.com/xsw632/ChipAgent --skill lint-xsw632

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill requires verilator.

What problem does it solve?

This Skill eliminates the tedious, error-prone manual process of reviewing generated Verilog code for syntax errors, style violations, and potential hardware design flaws, reducing the risk of downstream simulation failures and rework.

Core Features & Use Cases

  • Automated Verilog Linting: Runs Verilator lint-only checks on generated Verilog for any specified hardware module to catch syntax errors, style issues, and potential design flaws early in the development flow.
  • Prerequisite Validation: Automatically verifies that compiled Verilog exists for the target module, providing clear guidance to run compilation first if no generated code is found.
  • Use Case: After generating and compiling Chisel code for a custom 4-bit ALU, use this skill to quickly identify lint issues in the Verilog output before running time-consuming simulation and verification steps.

Quick Start

Use the lint skill to run Verilator lint checks on the generated Verilog for your target hardware module.

Frequently Asked Questions about lint

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I run Verilator lint checks on generated Verilog code?▼

You can automatically lint generated Verilog code by running Verilator lint-only checks on specified hardware modules. This skill validates syntax, identifies style violations, and detects potential design flaws using the project's existing lint script.

Can I use this to lint Verilog generated from Chisel?▼

Yes, you can lint Verilog generated from Chisel. This skill is specifically designed for hardware development workflows where Verilog is generated from higher-level hardware description languages like Chisel, serving as a pre-simulation validation step.

What do I need to have installed to run Verilator lint checks on my hardware modules?▼

You need the Verilator linting tool installed and accessible via your project's lint script. Additionally, you must have pre-compiled Verilog output for the target module located in your workspace directory before running the checks.

Why does the Verilog lint check fail when no generated code is found?▼

The Verilog lint check fails because it requires pre-compiled Verilog output for the target module in the workspace directory. The skill performs prerequisite validation and will provide clear guidance to run code compilation first if no generated Verilog is found.

When should I run automated Verilog linting in my hardware design workflow?▼

You should run automated Verilog linting after generating and compiling your hardware code, but before running time-consuming simulation and verification steps. This pre-simulation validation step catches syntax errors and design flaws early, reducing downstream rework.

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