skills.rest
xsw632
xsw632COMMUNITY
Explore all skills by this author →
GitHub

workflow

Generate simulation-verified Verilog from plain English hardware descriptions.

2|Updated Mar 16, 2026
Search Tags:#linting#simulation#hardware-design#verilog#chisel#testbench-generation
One-click install
npx skills add https://github.com/xsw632/ChipAgent --skill workflow-xsw632
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: workflow
Source: https://github.com/xsw632/ChipAgent/tree/main/skills/workflow
Command: npx skills add https://github.com/xsw632/ChipAgent --skill workflow-xsw632

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Manually developing digital hardware modules in Verilog requires deep expertise in hardware description languages, compilation toolchains, and verification workflows, leading to slow, error-prone development cycles for common digital components.

Core Features & Use Cases

  • End-to-end automated pipeline: Orchestrates the full hardware development workflow from natural language input to simulation-verified Verilog output, including requirement parsing, Chisel code generation, Verilog compilation, linting, testbench creation, simulation, and reporting.
  • Error recovery and validation: Includes structured spec validation, user confirmation steps, and automatic retry logic for compilation, linting, and simulation failures to reduce manual debugging work.
  • Use case: Hardware engineers can use this skill to generate and verify common digital modules like ALUs, priority encoders, or state machines in minutes instead of hours, eliminating manual Verilog coding and toolchain configuration.

Quick Start

Use the workflow skill to generate a simulation-verified 8-bit ALU with add, subtract, AND, OR, XOR, and SLT operations from a plain English description.

Frequently Asked Questions about workflow

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I generate Verilog from natural language hardware descriptions?▼

To generate Verilog from natural language, describe the target digital module in plain English. The workflow parses requirements, produces Chisel source code, compiles it into synthesizable Verilog, and outputs simulation-verified results.

Can I automate testbench generation and simulation for Verilog modules?▼

Yes, automated testbench generation and simulation execution are supported. The workflow creates testbenches for the generated Verilog, runs simulations, and produces verification reports to confirm module behavior without manual setup.

What is the best way to generate lint-clean Verilog without manual debugging?▼

The best way to produce lint-clean Verilog is using an automated pipeline with retry logic. The workflow compiles Chisel to Verilog, applies linting, and automatically retries on failures to reduce manual debugging effort.

Does this workflow support generating common digital modules like ALUs and state machines from plain English?▼

Yes, the workflow supports generating common digital modules like ALUs, priority encoders, and state machines. Provide a plain English description of the module's operations to produce verified Verilog output.

Why does Chisel source generation help with Verilog development errors?▼

Chisel source generation reduces Verilog development errors by automating code creation from structured specifications. The workflow validates specs, generates Chisel, and compiles to Verilog, eliminating manual hardware description language coding mistakes.

Do I need to manually configure compilation toolchains for Chisel to Verilog conversion?▼

No, manual toolchain configuration is not required. The workflow orchestrates the full Chisel to Verilog compilation pipeline, including linting and simulation, automatically handling toolchain setup and error recovery.

Related Skills

Explore More Software Engineering Skills→
xsw632xsw632
2

generate

Convert natural language hardware descriptions into compilable Chisel Scala source code.

Community
Intermediate
nandha-krishnan-mnandha-krishnan-m
4

verilog-hdl

Generate synthesizable Verilog RTL modules and debug race conditions, latch inference, and sim-vs-synth mismatches.

Community
Advanced
xsw632xsw632
2

lint

Run Verilator lint-only checks on generated Verilog for hardware modules.

Community
Intermediate
xsw632xsw632
2

compile

Compiles Chisel hardware modules into synthesizable Verilog via automated sbt builds.

Community
Intermediate