Convert natural language hardware descriptions into compilable Chisel Scala source code.
npx skills add https://github.com/xsw632/ChipAgent --skill generate-xsw632
Please help me install this Agent Skill. Skill: generate Source: https://github.com/xsw632/ChipAgent/tree/main/skills/generate Command: npx skills add https://github.com/xsw632/ChipAgent --skill generate-xsw632
Hardware engineers often waste hours manually writing Chisel Scala code for digital modules from natural language requirements, a process prone to human error that slows down hardware design iteration and prototyping.
Use the generate skill to create Chisel source code for a 4-bit priority encoder that takes 4 active-low input bits and outputs a 3-bit binary code representing the highest priority active input.
High-intent search queries and answers about installing and using this skill.
To generate Chisel code from natural language, describe your digital hardware module requirements in plain English. The system parses your text into validated JSON specifications with module ports, operations, and constraints for compilation.
Yes, you can use natural language to create Chisel Scala code for complex multi-module FPGA designs. The system supports generating both simple single modules and complex multi-module designs with top-level wiring for ASIC and FPGA development.
Natural language hardware design parsing works by converting your plain English descriptions into structured JSON specifications. It then presents the parsed spec for your approval, allowing quick modifications to ports or operations before final code generation.
You do not need to manually verify parsed hardware specs from scratch, but a user confirmation workflow presents the parsed specification for your approval. This allows you to quickly modify ports or operations before the final Chisel Scala source code is generated.
The best way to prototype digital logic modules in Chisel is to provide a plain English description of your hardware spec. The system parses requirements like an 8-bit ALU with add and subtract operations, confirms the spec, and outputs ready-to-use Chisel source code.
Yes, generated Chisel code integrates directly into your existing Scala project build system. The system outputs correctly structured Chisel files that are ready for use within your established hardware engineering project structure.
xsw632Generate simulation-verified Verilog from plain English hardware descriptions.
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etewe333Generate Scala/Chisel RTL code and build.sbt from RV32I hardware requirements.
xsw632Converts natural language hardware descriptions into Chime-compliant JSON specifications with validation and workspace setup.
