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riscv-code-generate

Generate Scala/Chisel RTL code and build.sbt from RV32I hardware requirements.

Updated Mar 18, 2026
Search Tags:#scala#chisel#riscv#rv32i#build.sbt#rtl-code-generation
One-click install
npx skills add https://github.com/etewe333/eda_first --skill riscv-code-generate
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: riscv-code-generate
Source: https://github.com/etewe333/eda_first/tree/main/.claude/skills/riscv-code-generate
Command: npx skills add https://github.com/etewe333/eda_first --skill riscv-code-generate

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This skill automates generation of Scala/Chisel code and a build.sbt for RV32I RTL pipelines, reducing manual coding effort.

Core Features & Use Cases

  • Generate module skeletons and interface definitions from hardware requirements.
  • Create fixed build.sbt configurations with required plugin versions and dependencies.
  • Provide end-to-end scaffolding including module class, IO, and a generator object, and place generated files under src/main/scala.

Quick Start

Provide the hardware function requirements and run the generator to produce the Scala/Chisel module and build.sbt.

Frequently Asked Questions about riscv-code-generate

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I generate Chisel RTL code for an RV32I processor automatically?▼

Chisel RV32I code generation automates Scala module skeleton and interface definition creation from hardware requirements. It outputs complete class structures with required imports and a generator object under src/main/scala.

What is the best way to set up a build.sbt file for a Chisel RV32I project?▼

A fixed build.sbt configuration for Chisel RV32I projects is generated automatically with required plugin versions and dependencies. This ensures the Scala source compiles correctly and produces Verilog-ready output.

Does the generated Chisel code for RV32I include compliance checks and test harnesses?▼

Generated Chisel code for RV32I includes compliance checks to ensure modules conform to the RV32I specification. The scaffolding focuses on module class, IO, and generator objects rather than producing separate test harnesses.

Can I use this to generate Verilog-ready Scala source from RV32I hardware requirements?▼

Yes, generating Verilog-ready Scala source from RV32I hardware requirements is supported. The process creates end-to-end scaffolding including module classes, IO definitions, and an end-of-file generator object for Verilog compilation.

What are the limitations of automating RV32I Chisel code generation for custom instruction sets?▼

Automating RV32I Chisel code generation is limited to the RV32I instruction set architecture. It applies fixed build.sbt version constraints and specific compliance checks, meaning custom instruction set extensions may not be supported.

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