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riscv-rv32i-check

Compares Chisel and Verilog ALU implementations against the RV32I spec.

Updated Mar 18, 2026
Search Tags:#verification#rtl#verilog#chisel#riscv#rv32i#alu
One-click install
npx skills add https://github.com/etewe333/eda_first --skill riscv-rv32i-check
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: riscv-rv32i-check
Source: https://github.com/etewe333/eda_first/tree/main/.claude/skills/riscv-rv32i-check
Command: npx skills add https://github.com/etewe333/eda_first --skill riscv-rv32i-check

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

Identifies and reports RV32I compatibility issues in generated ALU implementations by comparing Chisel sources and Verilog outputs against the RV32I ALU specification.

Core Features & Use Cases

  • RV32I conformance checks: Compare Chisel sources and Verilog outputs against the RV32I ALU spec, including funct3 mappings, sign handling, and zero-flag behavior.
  • Deviation reporting: Produce a structured report detailing any mismatches and suggested fixes.
  • Use Case: When validating a new RV32I ALU that is generated from Chisel, run this skill to ensure all mappings and results align with the standard before integration.

Quick Start

Run the RV32I ALU conformance check on a Chisel/Verilog project to generate a detailed RV32I compliance report.

Frequently Asked Questions about riscv-rv32i-check

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I verify RV32I ALU compliance in Chisel and Verilog?▼

Verify RV32I ALU compliance by comparing Chisel sources and Verilog outputs against the RV32I ALU specification, checking funct3 mappings, sign handling, and zero-flag behavior, and producing a structured deviation report for debugging.

What RV32I ALU compatibility issues are checked during verification?▼

RV32I ALU verification checks 32-bit arithmetic rules, signed and unsigned comparisons, funct3 mappings, sign handling, and zero-flag generation to enforce compliance with the RV32I standard.

How do I generate an RV32I deviation report for hardware debugging?▼

Generate an RV32I deviation report by running a conformance check on your Chisel or Verilog ALU implementation, which produces a structured report detailing any mismatches and suggested fixes for debugging and compliance.

Can I verify RV32I conformance for a Chisel-generated Verilog ALU?▼

Yes, you can verify RV32I conformance for a Chisel-generated Verilog ALU by comparing both the Chisel sources and Verilog outputs against the RV32I ALU specification to ensure all mappings and results align before integration.

Why does my RV32I ALU fail signed and unsigned comparison checks?▼

RV32I ALU signed and unsigned comparison checks fail when your Chisel or Verilog implementation violates 32-bit arithmetic rules, producing incorrect sign handling or zero-flag generation that deviates from the RV32I specification.

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