Run prebuilt RISC-V RTL simulation binaries with Verilator and capture results.
npx skills add https://github.com/etewe333/eda_first --skill riscv-sim-run
Please help me install this Agent Skill. Skill: riscv-sim-run Source: https://github.com/etewe333/eda_first/tree/main/.claude/skills/riscv-sim-run Command: npx skills add https://github.com/etewe333/eda_first --skill riscv-sim-run
本技能提供在 Verilator 环境下对 RISC-V RTL 设计进行仿真验证的自动化支持，简化从编译到日志分析的流程。
编译并确保可执行仿真文件存在后直接运行仿真以生成并保存日志。
High-intent search queries and answers about installing and using this skill.
RISC-V RTL simulation automation with Verilator works by executing prebuilt sim binaries from sim/build/V<module>. It automatically captures execution results and writes PASS/FAIL analysis logs to sim/logs/sim_result.log.
Running a Verilator testbench requires a prebuilt executable in sim/build/V<module>, a writable sim/logs directory for result storage, and .claude/env_info.json specifying msys_root and msystem environment paths.
Automated Verilator simulations save testbench results to sim/logs/sim_result.log. This specific log file contains the captured execution output necessary for PASS/FAIL analysis of the RISC-V pipeline modules.
Yes, you can validate RISC-V processor pipeline modules without manual checks using this automation. It executes the simulation binary and parses sim_result.log to provide immediate PASS/FAIL analysis for hardware verification.
Verilator simulation fails to find the msys_root path when .claude/env_info.json is missing or misconfigured. This file is strictly required to locate msys_root and msystem for executing the RISC-V sim binaries.
etewe333Validate RISC-V toolchain availability and environment fingerprint consistency.
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etewe333Generate Verilog from Scala/Chisel via sbt and lint with Verilator.
babywormRun UVM-based verification on RTL with commercial simulators and merge coverage artifacts.
