Agent Skills by etewe333
Showing 9 vetted skills indexed across 1 GitHub repositories.
etewe333riscv-log-save
Save RISC-V RTL simulation logs and Agent logs with timestamps.
etewe333riscv-env-check
Validate RISC-V toolchain availability and environment fingerprint consistency.
etewe333riscv-testbench-compile
Generate Verilator C++ testbenches and compile RV32I simulation executables.
etewe333riscv-code-generate
Generate Scala/Chisel RTL code and build.sbt from RV32I hardware requirements.
etewe333riscv-dir-init
Create a standardized directory structure for a RISC-V RTL project.
etewe333riscv-sim-run
Run prebuilt RISC-V RTL simulation binaries with Verilator and capture results.
etewe333skill-creator
Coordinate end-to-end Claude skill design from intent capture to SKILL.md drafting and eval-driven iteration.
etewe333riscv-rtl-lint
Generate Verilog from Scala/Chisel via sbt and lint with Verilator.
etewe333riscv-rv32i-check
Compares Chisel and Verilog ALU implementations against the RV32I spec.